Redundant line decoder master enable

Details Redundant line decoder master enable Redundant line decoder master enable

1995-06-19

1996-10-22

Westin, Edward P.

Electronic digital logic circuitry

Reliability

Redundant

365200, 36523006, 365108, H03K 19003

Patent

active

055680615

ABSTRACT:
A master enable circuit is provided which receives multiple enable signal inputs while matching the redundant decoder enable delay with decoder enable delay. A master enable circuit contains a hard coded master fuse, driver transistor, and a multiple input logic gate. A blown master fuse forces the driver output to an enable state. When the proper select signals are then received by the logic gate, the decoder is enabled to allow selection of the redundant row without introducing a mismatch of redundant and normal line select times.

REFERENCES:
patent: 4714839 (1987-12-01), Chung
patent: 5257228 (1993-10-01), Sukegawa
patent: 5262994 (1993-11-01), McClure
patent: 5274594 (1993-12-01), Yanagisawa
patent: 5311472 (1994-05-01), Ota
Toshiba Circuit Diagram, Jan. 1992.

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