Redundant decoder utilizing address signal and burst length

Details Redundant decoder utilizing address signal and burst length Redundant decoder utilizing address signal and burst length

1997-06-16

1999-05-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36518908, 36523006, G11C7/00

Patent

active

059056819

ABSTRACT:
The redundancy decoder circuit is capable of receipt of burst length information of address signals for first reading out an address of two addresses to be multi-selected and also judging address to be substituted in accordance with other address to be concurrently read out by means of switching, by the burst length signal, the combination logic of the lower bits of the address already prepared.

REFERENCES:
patent: 5499216 (1996-03-01), Yamamoto
patent: 5517458 (1996-05-01), Koshikawa
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5673227 (1997-09-01), Engles et al.

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