Redundant decoder having fuse-controlled transistor

Details Redundant decoder having fuse-controlled transistor Redundant decoder having fuse-controlled transistor

2000-04-12

2001-05-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S121000, C326S095000, C326S098000, C326S010000, C326S013000, C327S525000, C327S526000

Reexamination Certificate

active

06236241

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a redundant decoder, and more particularly to a redundant decoder having a fuse-controlled transistor.
2. Description of the Prior Art
Presently, there is a high demand for high-density memory such as DRAM arrays. One way to increase the yield is to design of redundant memory arrays. By repairing defective memory devices, the yield is increased. As shown in
FIG. 1
, a memory array generally comprises several row word lines like W
0
and W
1
of
FIG. 1
, and several column bit lines like BS
0
of
FIG. 1
, locating the stored data address in the memory. In order to prevent the entire memory array from being discarded due to defective rows or the defective columns, a redundant device is installed in most current memory arrays. For example, if rows W
0
and W
1
are defective, then redundant rows RW
0
and RW
1
are used, or if column bit line BS
0
is defective redundant column bit line RBS
0
is used.
In addition, as illustrated in
FIG. 2
, a redundant decoder
2
of a conventional redundant device comprises the following:
A discharging device, such as an evaluating NMOS transistor
13
coupled to ground Vss having a gate terminal G
1
for inputting an evaluating signal ø and a drain terminal coupled to source terminal of a pair of MOS transistors. The NMOS transistor
13
is turned on by the evaluating signal ø at an evaluating cycle EV, thereby providing a discharging path
11
used to discharge to ground Vss.
A precharging device, such as a PMOS transistor
10
coupled to a power source Vcc having a gate terminal G
2
for inputting a precharging signal npre. The PMOS transistor
10
is turned on by the precharging signal npre at a precharging cycle PC, thereby providing a precharging voltage X to the power source Vcc.
A pair of fuses
12
and
14
having a first terminal A and two second terminals B
1
, B
2
, wherein, first terminal A has been precharged at the precharging voltage X on the precharging device
10
.
A pair of MOS transistors, such as NMOS transistors
16
,
18
having drain terminals B
3
, B
4
, a source terminal C, and gate terminals G
3
, G
4
. Drain terminals B
3
, B
4
couple the second terminals B
1
, B
2
of the fuse
12
,
14
, respectively. Gate terminals G
3
, G
4
are used to receive the pair of complementary address bit signals cx, cxn, and whether the NMOS transistors
16
,
18
are turned on or not can be decided by the logic value 1 or 0 of the pair of complementary address bit signals cx, cxn. Source terminal C couples to the evaluating device
13
.
According to the redundant decoder
2
, when memory cells of a memory array have defects, the corresponding defective address bit, such as the fuse
14
of cxn, has to be blown down (by laser) in order to form a open loop, but the fuse
12
remains in a closed loop. Later, when the address bit of an address signal cx=0 and its complementary address bit cxn=1 are inputted, transistor
18
turns on and transistor
16
turns off so that discharging path
11
is unavailable. Meanwhile, the potential of the first terminal A of the fuse
12
and
14
has been maintained at the precharging voltage X level on logic 1. Hence decision circuit
15
outputs a redundant flag according to the precharging voltage X level of logic 1, thereby recognizing the representing address bit of the inputting address signal as the defective address bit and replacing with redundant memory cell corresponding to the inputted defective address.
On the other hand, when the address bit cx=1 of the address signal and its complementary address bit cxn=0 are inputted, transistor
18
turns off and transistor
16
turns on so that discharging path
11
is available. Meanwhile, the potential of the voltage of the first terminal A of fuse
12
and
14
will be pulled down to ground Vss along the discharging path
11
. Hence decision circuit
15
will not output the redundant flag, thereby recognizing the representing address bit of the inputting address signal as a non-defective address bit.
However, the problem of a conventional redundant decoder
2
is that fuse
12
and fuse
14
are located on the discharging path. Fuse resistance is not easily controlled. Therefore, the discharging speed is influenced. Moreover, the entire circuit may break down.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a redundant decoder having a fuse-controlled transistor, to preventing the discharging speed from being influenced by the fuse resistance and avoiding circuit breakdown.
The present invention achieves the above described object by providing a redundant decoder having a fuse-controlled transistor. The redundant decoder having fuse-controlled transistor of the present invention comprises: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage; a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive a pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals; a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; and a fuse device, having a fuse which is coupled to the bistable device that decides the logic values of the pair of complementary signals by whether the fuse is burnt down or not.
The advantage of the redundant decoder of the present invention is that the transistors replace the fuses in the discharging path. Hence, the operation of the redundant decoder of the present invention is unaffected by fuse resistance, also the number of fuses is reduced to about half. In addition, the redundant decoder can perform the pretest without blowing down fuses.


REFERENCES:
patent: 5387823 (1995-02-01), Ashizawa
patent: 5619469 (1997-04-01), Joo
patent: 5712588 (1998-01-01), Choi et al.
patent: 5862087 (1999-01-01), Lee
patent: 6087890 (2000-07-01), Kim
patent: 6125069 (2000-09-01), Aiki

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