Redundant decoder circuit

Details Redundant decoder circuit Redundant decoder circuit

2002-01-14

2003-03-04

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S200000

Reexamination Certificate

active

06529420

ABSTRACT:

This application claims priority from Korean patent application No. 2001-2210 filed Jan. 15, 2001 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to redundant decoder circuits for semiconductor memory devices, and more particularly, to redundant decoder circuits that store defective cell addresses in electrically erasable and programmable memory.
2. Description of the Related Art
The manufacturing processes for semiconductor memory devices sometimes produce devices having defective memory cells due to particles, bridges, or oxide defects. These defective memory cells reduce the production yield. One technique for improving the production yield is to repair defective cells by manufacturing the device with a redundant memory cell array in addition to a main memory cell array. If a defective cell is identified in the main memory cell array, it is replaced with a redundant memory cell from the redundant memory cell array.
To implement such a redundancy technique, the address of the defective memory cell, i.e., a repair address, must be stored on the device.
FIG. 1
is a diagram showing a prior art circuit for storing a repair address. Referring to
FIG. 1
, a repair address storage block
1
is formed from a resistor R
1
connected between power supply voltage Vcc and a node N
0
for charging the node N
0
; pairs of fuses F
0
,FB
0
through Fk,FBk in which one end of each fuse is connected to the node N
0
; pairs of transistors MN
0
,MNB
0
through MNk,MNBk for discharging the node N
0
; a latch L
1
; and an inverter INV
1
.
Each of the fuse pairs F
0
,FB
0
~Fk,FBk stores one-bit of the address of a defective cell in a main memory cell array. The node N
0
is high when the address stored in the fuses corresponds to external address data A
0
,NA
0
~Ak,nAk. If the addresses do not correspond, the node N
0
is discharged to a low level. Thus, if the signal INFO provided through the latch L
1
and the inverter INV
1
is high, the external address is that of the defective cell in the main memory cell array.
The repair address storage block
1
illustrated in
FIG. 1
is able to store only one repair address. A plurality of repair address storage blocks are required to store a plurality of repair addresses.
As described above, the conventional repair address storage block
1
utilizes fuse pairs F
0
,FBO~Fk,FBk in order to store the address of a defective cell in a main memory cell array. However, circuits using fuses require long test times. Known laser equipment used for cutting fuses is not only expensive, but also requires long test times, thereby increasing the manufacturing cost of semiconductor memory devices.
A further problem with the prior art is that it is impossible to test the redundant memory cell array for defects. This is because fuses must be laser cut in order to access the redundant memory cell array. However, once the fuses are cut, they cannot be restored, and thus, the redundant cell array cannot be tested. In addition, the laser fuses require a large topological area in the semiconductor memory device, and pads be open to be cut. Accordingly, the total layout dimension is increased.
SUMMARY OF THE INVENTION
One aspect of the present invention is a redundant decoder circuit comprising an address storage circuit having a plurality of electrically erasable and programmable memory cells arranged to store address data corresponding to a defective cell; and a comparison circuit coupled to the address storage circuit and adapted to generate an information signal responsive to the address data and an externally applied address. A redundant enable control unit can be adapted and arranged to enable and disable the redundant decoder circuit responsive to the state of an electrically erasable and programmable memory cell that indicates whether a main memory cell array has any defective cells.
Another aspect of the present invention is a memory core having main memory cells and redundant memory cells; a multiplexer coupled to the memory core and adapted to select signals from either main memory cells or redundant memory cells responsive to a selection signal; and an address storage block adapted to store an address of a defective memory cell and generate an information signal for generating the selection signal, wherein the address storage block comprises electrically erasable and programmable memory adapted to store the address of the defective memory cell.
A further aspect of the present invention is a method for accessing a memory core having main memory cell arrays and redundant memory cell arrays, the method comprising: storing address data corresponding to a defective memory cell in electrically erasable and programmable memory; comparing the address data to an externally applied address, thereby generating an information signal; and selecting either a main memory cell or redundant a memory cell responsive to the information signal.
An additional aspect of the present invention is a method for testing a memory device having main memory cells and redundant memory cells, the method comprising: programming address data corresponding to a main memory cell in an electrically erasable and programmable memory cell; accessing a redundant memory cell responsive to the address data; testing the redundant memory cell; and performing a repair operation on the memory device.


REFERENCES:
patent: 5598373 (1997-01-01), Wada et al.
patent: 5604702 (1997-02-01), Tailliet
patent: 5815449 (1998-09-01), Taura

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