Redundant decision circuit for semiconductor memory device

Details Redundant decision circuit for semiconductor memory device Redundant decision circuit for semiconductor memory device

2000-08-09

2001-07-03

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S096000

Reexamination Certificate

active

06256239

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor memory device, and, more particularly, to a redundant decision circuit for specifying a redundant memory cell in a memory cell array when a normal cell is defective.
To improve yield, a semiconductor memory device includes a redundant function that replaces a defective cell with a redundant cell in a cell array in the manufacturing process. For the redundant function, a redundant decision circuit is provided which generates a redundant signal in accordance with the cutting of a fuse of the defective cell.
FIG. 1
is a schematic block diagram of a first conventional redundant decision circuit
100
. A one-shot pulse generation circuit generates a control signal &phgr;
1
having a power supply VDD level after a predetermined time has elapsed from the start-up of the power supply VDD. The control signal &phgr;
1
is supplied to the gate of a P-channel MOS transistor Tr
1
. The source of the transistor is connected to the power supply VDD, and the drain (a node N
1
) is connected to a power supply Vss via a fuse
2
. The node N
1
is connected to an input terminal of a hold circuit
3
. The hold circuit
3
supplies complementary redundant signals R, /R to a row decoder (not shown) in accordance with a potential at the node N
1
after power-on. For example, when the redundant signal R goes high and the redundant signal /R goes low, the row decoder stops access to the defective cell in a memory cell array and accesses the previously specified redundant cell.
FIG. 2
is a waveform diagram of the power supply and control signal in the first conventional redundant decision circuit
100
. When the power supply VDD is turned on, the control signal &phgr;
1
rises to the power supply VDD level after the predetermined delay time has elapsed from the start-up of the power supply VDD. The transistor Tr
1
is turned on for a predetermined time t
1
after the potential difference has become greater than the threshold and until the potential difference between the power supply VDD and control signal &phgr;
1
becomes smaller than a threshold of the transistor Tr
1
.
When the fuse
2
is not cut, the drain current of the transistor Tr
1
flows in the power supply Vss via the fuse
2
, and the node N
1
is maintained at substantially the low potential power supply Vss level. The hold circuit
3
maintains the node N
1
at an L level and outputs a redundant signal R Low and a redundant signal /R High. The hold circuit
3
maintains the output states of the redundant signals R, /R even if the transistor Tr
1
is turned off after the predetermined time t
1
has elapsed.
When the fuse
2
is cut, the node N
1
rises to substantially the power supply VDD level for the predetermined time t
1
. Hereupon, the hold circuit
3
outputs the redundant signal R High and the redundant signal /R Low. The hold circuit
3
maintains the output states of the redundant signals R, /R even if the transistor Tr
1
is turned off after the predetermined time t
1
has elapsed.
In the first conventional redundant decision circuit
100
, as shown by dotted lines in
FIG. 2
, when the start-up of the power supply VDD supplied to the source of the transistor Tr
1
is slow under the cut state of the fuse
2
, the on time t
1
of the transistor Tr
1
is shortened. This is because the control signal &phgr;
1
rises before the potential difference between the gate and source of the transistor Tr
1
becomes sufficiently greater than the threshold. Hereupon, a sufficient drain current does not flow to the transistor Tr
1
and the potential at the node N
1
does not rise sufficiently. As a result, although the fuse
2
is cut, the hold circuit
3
outputs the redundant signal R Low and the redundant signal /R High. Moreover, when a leak current flows in the cut fuse
2
, the potential rise at the node N
1
is further suppressed and the probability of causing an incorrect decision increases.
To overcome such a problem, the on time ti of the transistor Tr
1
could be prolonged by further delaying the rising edge of the control signal &phgr;
1
. However, in this case, the penetration current flowing in the power supply Vss from the power supply VDD via the transistor Tr
1
and the fuse
2
increases. Moreover, the delay time of the one-shot pulse generation circuit
1
is set using a MOS (metal oxide semiconductor) capacitance. Accordingly, to prolong the delay time, the capacitance needs to be increased. However, a large MOS capacitance increases the circuit area of the one-shot pulse generation circuit
1
.
FIG. 3
is a schematic block diagram of a second conventional redundant decision circuit
200
. A control signal &phgr;
2
generated by a one-shot pulse generation circuit
4
is supplied to the gate of an N-channel MOS transistor Tr
2
. The source of the transistor Tr
2
is connected to the power supply Vss, and its drain (a node N
2
) is connected to the power supply VDD via the fuse
2
. An input terminal of the hold circuit
3
is connected to the node N
2
. When the redundant signal R goes low and the redundant signal /R goes high, the row decoder (not shown) stops access to the defective cell in the memory cell array and accesses the previously specified redundant cell.
FIG. 4
is a waveform diagram of the power supply and control signal of the second conventional redundant decision circuit
200
. When the power supply VDD is turned on, after a predetermined time has elapsed from the start-up of the power supply VDD, the control signal &phgr;
2
having the power supply VDD level is generated. The transistor Tr
2
is turned on for the predetermined time t
2
until the potential difference between the power supply Vss and the control signal &phgr;
2
becomes smaller than the threshold of the transistor Tr
2
after the potential difference has become greater than the threshold.
When the fuse
2
is not cut, a drain current is supplied from the power supply VDD to the transistor Tr
2
via the fuse
2
, and the node N
2
is maintained at substantially the power supply VDD level in accordance with the resistance ratio between the fuse
2
and the transistor Tr
2
. The hold circuit
3
maintains the node N
2
at the H level and outputs the redundant signal R High and the redundant signal /R Low.
When the fuse
2
is cut, the potential at the node N
2
drops to substantially the power supply Vss level. Hereupon, the hold circuit
3
outputs the redundant R Low and the redundant signal /R High.
In the second conventional redundant decision circuit
200
, when a leak current flows in the cut fuse
2
, the potential drop at the node N
2
is suppressed. Hereupon, although the fuse
2
is cut, the hold circuit
3
may output the redundant signal R High and the redundant signal /R Low.
To overcome such a problem, the on time t
2
of the transistor Tr
2
could be prolonged by further delaying the falling edge of the control signal &phgr;
2
. However, in this case, the penetration current flowing in the power supply Vss from the power supply VDD via the fuse
2
and the transistor Tr
2
increases. Moreover, to prolong the delay time of the one-shot pulse generation circuit
4
, a MOS capacitance needs to be increased, which increases the circuit area of the one-shot pulse generation circuit
4
.
It is an object of the present invention to provide a redundant decision circuit that prevents an incorrect decision when a fuse is cut, without increasing power consumption and circuit area.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, a redundant decision circuit is provided that includes a switching element, a switching driver connected to the switching element for driving the switching element, a fuse, and a load circuit connected in series with the fuse. One of the fuse and the load circuit is connected to the switching element. A hold circuit is connected to a node between the switching element and one of the fuse and the load circuit, latches a potential at the node and generates a redundant decision signal.
In a second aspect of

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