Redundant configuration memory systems and methods

Details Redundant configuration memory systems and methods Redundant configuration memory systems and methods

2009-09-22

2010-06-29

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

Reexamination Certificate

active

07746107

ABSTRACT:
In one embodiment, a programmable logic device includes a plurality of configuration memory cells and at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells (e.g., identified as a defective memory cell). An address shift register within the device is adapted to provide programming signals to the plurality of configuration memory cells via wordlines. A data shift register within the device is adapted to provide configuration data to the plurality of configuration memory cells via bitlines. The data shift register is further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

REFERENCES:
patent: 7254069 (2007-08-01), Haraguchi et al.
patent: 7505319 (2009-03-01), Wu et al.

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