Redundant column substitution architecture with improved column

Details Redundant column substitution architecture with improved column Redundant column substitution architecture with improved column

1985-12-20

1987-09-01

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 1300

Patent

active

046913009

ABSTRACT:
An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.

REFERENCES:
patent: 4459685 (1984-07-01), Sud et al.
patent: 4471472 (1984-09-01), Young

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