Redundant column read in a memory array

Details Redundant column read in a memory array Redundant column read in a memory array

2007-11-13

2007-11-13

Chung, Phung My (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000, C365S201000

Reexamination Certificate

active

11131017

ABSTRACT:
A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may be read speculatively after a particular set of the highest order address bits are received. After a complete address is received, any requirement for substitution of redundant memory bits is known. If no substitution is required, the regular memory contents are read. Any requirement for a substitution of memory bits may require replacement of the entire location. A regular read operation continues after the first location is read. In this way, complete and correct data for the memory location are available after receipt of a read instruction with no additional delay for including any required redundant memory bits.

REFERENCES:
patent: 6185709 (2001-02-01), Dreibelbis et al.
patent: 6571348 (2003-05-01), Tsai et al.
patent: 6603688 (2003-08-01), Hasegawa et al.

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