Redundant circuits and methods therefor

Details Redundant circuits and methods therefor Redundant circuits and methods therefor

1997-06-20

1998-11-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

058319166

ABSTRACT:
A method for replacing defective elements of a memory array. The method includes forming a first redundant circuit, which in turn includes forming a first plurality of address fuses. The first plurality of address fuses are configured to specify, when set, an address of one of the defective elements. The method further includes forming a first plurality of address latches, respective ones of the first plurality address latches being coupled with respective ones of the first plurality of address fuses. There is further included forming a first redundant element. Additionally, the method includes forming a first decoding logic circuit. The first decoding logic is coupled to the first plurality of address latches and the redundant element. The first decoding logic circuit is configured to ascertain during operation of the memory array whether a bit pattern stored in the first plurality of address fuses differs from a first predefined value and to place the first redundant element in a replacement mode if the bit pattern differs from the predefined value. The replacement mode enables the first redundant element to be used in place of the one of the defective elements during operation.

REFERENCES:
patent: 5596535 (1997-01-01), Mushya et al.
patent: 5621691 (1997-04-01), Park

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