Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-12-19
2002-11-12
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030
Reexamination Certificate
active
06480428
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to a redundant circuit that may be used to replace a defective memory cell in a memory device.
Memory devices are integral to computer systems and many electronic circuits. Continuous improvements in the operating speed and computing power of central processing units (CPUs) enable the operation of an ever-greater variety of applications, many of which require larger and faster memories. Larger memories are characterized by having more memory cells to store more bits of data.
The manufacturing process for larger memory devices is very challenging, especially as the number of memory cells increases and the size of the memory cells decreases. In fact, it is common to have one or more defective memory cells in any given manufactured memory device. For costs and other considerations, it is impractical to reject an entire memory device if only a few of the cells are actually defective. Thus, to increase production yields, redundant memory cells are typically fabricated within each memory device. During the production and/or testing phase, the cells in the memory device are tested and any cell identified as defective is replaced with a redundant cell.
To replace a defective cell with a redundant cell, the address of the defective cell is effectively changed such that if the address of this cell is selected, the redundant cell is internally selected in its place. In this way, if the address of the defective cell is selected during normal device operation, the alternative lines (e.g., the word line and/or column select line) for the redundant cell are selected instead of the lines for the defective cell.
Several techniques are available to “program” the address of a redundant cell to replace a defective cell. In one technique, the address of the redundant cell is programmed by blowing selective ones of a set of fuses provided for the cell. Another “master” fuse may also be blown to indicate that the redundant cell has been programmed for use. In another technique, the address of the redundant cell is programmed by shorting selective ones of a set of anti-fuses provided for the cell.
Fuses are typically fabricated with metal lines or poly-silicon, and are typically blown using a laser (which is a preferred method) or some other technique. For the laser technique and since a fuse needs to be physically exposed to the laser to be blown, the programming of the fuses for a redundant memory cell is typically only performed during wafer testing (i.e., prior to packaging the memory device). In contrast, an anti-fuse can be electrically shorted, and the programming of the anti-fuses for a redundant cell is typically performed during package testing.
Fuses are thus not as flexible because they can only be programmed during wafer testing, but their smaller size makes them attractive. Anti-fuses are more flexible and can be programmed during final testing, but their larger size (e.g., 3 to 4 times the die area of fuses) makes them more costly.
For flexibility and improved production yields, a memory device may be fabricated with one set of redundant memory cells that can be programmed with fuses and another set of redundant cells that can be programmed with anti-fuses. The redundant cells with fuses can be used to replace defective cells detected during wafer testing, which may account for approximately 90% of all defective cells on the memory device. And the redundant cells with anti-fuses can be used to replace any remaining defective cells during package testing (i.e., defective cells not detected or replaced during wafer testing).
One of the challenges in the design of a memory device is the selection and allocation of the number of redundant memory cells with fuses and anti-fuses to be included in the device. If too many redundant cells are provided but not used, the additional die area for these cells and their support circuitry unnecessarily increases the costs for the memory device. If not enough redundant cells are provided, more defective devices that cannot be repaired may be thrown out, which would decrease production yields and also increase costs. For a given number of redundant cells, if more redundant cells with fuses are allocated, the number of defective cells that may be repaired during package testing is reduced. And if more redundant cells with anti-fuses are allocated, the larger size of the anti-fuses increases the die area and costs of the device.
As can be seen, a redundant circuit that can be effectively used to replace a defective memory cell in a memory device, and which may improve the yields and costs of the memory device, is highly desirable.
SUMMARY OF THE INVENTION
The invention provides a redundant circuit that includes a combination of fuses and anti-fuses, and which may be used during various phases of the manufacturing process (e.g., during wafer test or final test) to replace a defective circuit. For an implementation in a memory device, the redundant circuit includes a “fuse and anti-fuse” circuit, an address comparator, and a redundant cell. In a general sense, the redundant circuit includes (1) a replacement circuit (e.g., a memory cell) that can be used to replace a defective circuit, and (2) supporting circuitry for the replacement circuit, which includes a combination of fuses and anti-fuses. The redundant circuit of the invention can be efficiently fabricated within a memory device, and may also be used for other circuits and applications.
An embodiment of the invention provides a redundant circuit that includes a replacement circuit and a support circuit. The replacement circuit (e.g., a redundant memory cell) is configurable to replace a defective circuit. The support circuit is configurable to provide a control signal (e.g., to activate a word line) for the replacement circuit and further includes at least one fuse and at least one anti-fuse. The fuse or anti-fuse may be programmed to provide a programmed value (e.g., a programmed address) for the replacement circuit.
In one specific design, the support circuit may be designed to include first, second, and third circuits (e.g., a anti-fuse circuit, a fuse latch, and an address comparator, respectively). The first circuit includes the anti-fuse, and is further configurable to program the anti-fuse or sense the state of anti-fuse. The second circuit includes the fuse, and is further configurable to sense the state of the fuse, receive the sensed state of the anti-fuse, and provide the programmed value indicative of the sensed states of the fuse and anti-fuse. The third circuit receives the programmed value, compares the programmed value with an external value (e.g., an external address), and provides the control signal for the replacement circuit based on the result of the comparison and the status of the redundant circuit (i.e., whether or not it has been programmed to replace the defective circuit).
The redundant circuit and methods described herein can be advantageously implemented within an integrated circuit, a DRAM device, and other devices. Various other aspects, embodiments, and features of the invention are described in further detail below.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
REFERENCES:
patent: 5596536 (1997-01-01), Koh
patent: 5923682 (1999-07-01), Seyyedy
patent: 6201733 (2001-03-01), Hiraki et al.
patent: 6282689 (2001-08-01), Seyyedy
Kim Jae-Hyeong
Zheng Hua
Dinh & Associates
Ho Hoai
Winbond Electronics Corporation
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