Redundant circuit configuration for an integrated semiconductor

Details Redundant circuit configuration for an integrated semiconductor Redundant circuit configuration for an integrated semiconductor

1995-08-14

1997-08-12

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 800

Patent

active

056572794

ABSTRACT:
A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output. The comparator compares the second partial address stored in memory in one of the address circuits with the applied second partial address, at the applied activation signal of the one address circuit. The comparator supplies an enable signal at the first output of the address comparator if the two partial addresses match. Redundance decoders are triggered by the enable signal.

REFERENCES:
patent: 5293339 (1994-03-01), Suzuki et al.
patent: 5293564 (1994-03-01), Sukegawa et al.
IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17, (Horiguchi et al.) "A Flexible Redundancy Technique for High-Density DRAM's".

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