Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-11-12
1998-11-10
Mai, Son
Static information storage and retrieval
Read/write circuit
Bad bit
36518509, G11C 2900
Patent
active
058354263
ABSTRACT:
The present invention includes a redundant circuit for addressing redundant memory cells. The redundant circuit solves a problem of a conventional redundant circuit caused by injection of electrons into and leakage of electrons from a floating gate of a non-volatile memory cells provided for respective bits of the addressing circuit of the redundant circuit. The redundant circuit has a timer that counts an elapsed time from power-on of the redundant circuit. The timer produces a timing signal when a fixed duration time period has elapsed. A breaker breaks the application of a supply voltage to the gate of a non-volatile memory cell in response to the timing signal.
REFERENCES:
patent: 4382249 (1983-05-01), Jacobsthal
patent: 5018104 (1991-05-01), Urai
patent: 5233566 (1993-08-01), Imamiya et al.
patent: 5300840 (1994-04-01), Drouot
patent: 5481498 (1996-01-01), Han
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
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