Redundant bus bridge systems and methods using selectively synch

Details Redundant bus bridge systems and methods using selectively synch Redundant bus bridge systems and methods using selectively synch

1998-04-17

1999-11-23

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, 713400, 713501, 370285, 370402, G06F 1300, G06F 1342, G06F 104, H04L 700

Patent

active

059918446

ABSTRACT:
A redundant bus bridge system for communicating between a first bus and a second bus includes a first clock generator operative to produce a first clock signal and a second clock generator operative to produce a second clock signal. A first bus bridge, e.g., a first RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. A second bus bridge, e.g., a second RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. According to aspects of the present invention, the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the second clock signal when the second bus bridge is operational, and the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the first clock signal when the second bus bridge is non-operational.

REFERENCES:
patent: 5210858 (1993-05-01), Jensen et al.
patent: 5434996 (1995-07-01), Bell
patent: 5838995 (1998-11-01), Chen et al.

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