Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-08-04
2001-06-05
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C160S114000, C160S113000, C160S117000
Reexamination Certificate
active
06243795
ABSTRACT:
TECHNICAL FIELD
The invention relates to the field of redundant data storage systems, and in particular to a data storage system architecture having a redundant, asymmetrical disk cache.
BACKGROUND OF THE INVENTION
A well known disk array system architecture is referred to as “redundant array of independent/inexpensive disks” (RAID). The RAID system architecture provides a large amount of data storage in a reasonably reliable manner. Several popular RAID system architectures are set forth in the paper entitled “A Case for Redundant Arrays of Inexpensive Disks (RAID)”, Patterson et al., Proc. ACM SIGMOD, June 1988. These architectures include RAID-1, RAID-2, RAID-3, RAID-4 and RAID-5. U.S. Pat. No. 5,526,482 entitled “Storage Device Array Architecture With Copyback Cache” briefly discusses each of these architectures, and in the interest of brevity a similar discussion will not be repeated herein.
In general, each of the RAID system architectures includes a plurality of disks that are controlled by a RAID disk controller. When a central processing unit (CPU) sends information to the disk controller for storage on disk, the controller directs how the information shall be stored on the plurality of disks to ensure that a failure of any one of the disks will not cause the system to loose information.
Modern disks are impressively reliable, with a Mean Time To Failure (MTTF) of up to about 1 million hours. Such a low failure rate, coupled with the inherent redundancy provided by the RAID system architecture provides a Mean Time To Data Loss (MTTDL) of around several hundreds of millions of hours in a typical RAID-5 system architecture. However, this is not the system MTTDL, since the reliability of the system is only as good as the reliability of its most unreliable component.
Many RAID systems employ a single cache in front of the plurality of disks. However, a single cache creates a single point failure mode which could disable the entire RAID system and cause the loss of data. Typical RAID caches use an NVRAM cache (e.g., battery backed RAM) which has a MTTF of only about 15,000 hours. Therefore, failure of the NVRAM cache results in a significantly higher risk of data loss in comparison to the risk associated with a disk failure.
To overcome this reliability problem, some high-end RAID systems use dual-copy caches (i.e., a primary cache and a backup cache) so a failure in one cache does not cause the loss of data. That is, the other cache is intact which ensures the integrity of the data stored on disk. When a write request arrives from the CPU, the controller writes the data independently into the two caches. Although the use of dual-copy caches overcomes the reliability problem of the single-copy cache, the high cost of NVRAM makes dual-copy caches prohibitively expensive, particularly for large caches.
Therefore, there is a need for a redundant, inexpensive write cache for use in a data storage system, including RAID systems.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data storage system which employs an inexpensive, redundant write cache.
Briefly, according to the present invention, a data storage system includes redundant write caches, a disk controller and an array of disks. One of the redundant write caches is a primary write cache and another is a backup write cache having a hybrid memory structure comprising a cache-disk space mapped to at least one of the disks.
The cache-disk space may be located on a single disk within the disk array, or distributed over a number of the plurality of disks in the array. In one embodiment, the array of disks may be configured as a RAID architecture.
The data storage system of the present invention preferably employs a conventional, fast-write-fast-read primary write cache and a non-volatile, hybrid memory backup write cache. The backup write cache includes NVRAM, and small and random writes are buffered in a least recently used (LRU) cache located in the NVRAM. If the LRU cache is full, LRU data blocks in the LRU cache are transferred into a segment buffer which is also located in the backup cache NVRAM to make room for new write requests. When the segment buffer is full, its entire contents are written into the cache-disk space. Notably, combining the data from smaller writes into a block of data for a larger write reduces the number of smaller writes, and the segment buffer is quickly made available for additional requests so the two level backup cache appears to a host CPU as a large NVRAM. As a result, the backup write cache may achieve the same write speed as the primary cache.
The redundant write caches are asymmetric since the primary write cache and the backup write cache have different structures.
The system is relatively inexpensive since the amount NVRAM in the backup cache is relatively small, ranging from hundreds of KB to several MB, and the cost of the disk space for the cache-disk space is significantly less than a large amount of NVRAM.
Advantageously, the caching arrangement of the present invention has a significant reliability advantage over conventional single NVRAM write caches, and a cost advantage over dual-copy NVRAM caches. In addition, the present invention provides a cost-effective architecture for very large write caches capable of masking the effects of small writes for high-end data storage systems that would otherwise have to use dual-copy, identical NVRAM caches.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
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Hu Yiming
Yang Qing
Kim Matthew
Peugh B.
Samuels, Gauthier & Stevens, LLP.
The Board of Governors for Higher Education, State of Rhode Isla
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