Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-04-28
2004-02-24
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S194000
Reexamination Certificate
active
06697289
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to redundancy circuits for semiconductor memory devices, and more particularly to redundancy address setting circuits for semiconductor memories.
BACKGROUND OF THE INVENTION
The storage capacity of semiconductor memory devices has continued to increase at a remarkable rate. This is particularly true for high-density memory devices such as dynamic random access memories (DRAMs). The increase in storage capacity is due to a number of factors, including advancements in processing technology and/or reductions in the size of various features within a DRAM. Reduced features include smaller spacings between repeated structures (smaller “pitch”), as well as reductions in the size of particular components, such as conductive line widths, transistors, capacitors, and the like.
Due to the great number of memory cells and high complexity of most semiconductor memory devices, it can be very difficult to consistently manufacture devices that are completely free of defects. If all semiconductor devices having defects were completely discarded, the manufacturing yield of such devices would be significantly lowered. In order to increase fabrication yield, most semiconductor devices include some sort of redundancy scheme.
A redundancy circuit typically replaces one circuit element (such as a defective memory cell) with another (such as a redundant memory cell). In operation, when an address is applied to a memory device that corresponds to a defective memory cell, a redundancy circuit can detect such an address and prevent the defective memory cell from being accessed. Instead, the redundancy circuit can provide access to a redundant memory cell. An access to a redundant memory cell can be indistinguishable from an access to a “normal” memory cell.
In this way, even if a semiconductor memory device includes defective memory cells (due to uncontrollable process variation, for example), it can still be fully functional through the use of redundancy circuits. This can allow semiconductor devices with defective memory cells to be packaged and provided as working devices. Consequently, the overall fabrication yield can be increased.
As noted above, a redundancy circuit can continuously monitor externally applied address values. Such external address values can be compared with known defective addresses (addresses corresponding to defective memory cells) to determine when an access should be switched to a redundant memory cell. Information for identifying defective addresses is typically stored in a programming circuit. Many programming circuits include fusible links (fuses) for storing defective address information.
An example of a programming circuit is set forth in Japanese Laid Open Patent Application No. 8-96594. In the programming circuit of Japanese Laid Open Patent Application No. 8-96594, two fuse elements are allocated for each bit of an applied external address. According to the defective address bit value, one of the two fuses is opened. Thus, for each bit of a defective address, one of two fuses will be opened to thereby “store” the defective address for the redundancy circuit.
A drawback to the approach set forth in Japanese Laid Open Patent Application No. 8-56594 is that two fuses are required for each address bit. For example, if a semiconductor memory device received a 10-bit address, 20 fuses would be required to program one defective address. Consequently, in a semiconductor device that is capable of replacing 1,024 defective addresses, as many as 2,048 fuses would be required. Fuses are typically devices of relatively large width. Thus, a large number of fuses can increase the overall area of a memory device. Such increases in area can translate into higher manufacturing costs.
One way to overcome the above drawbacks is to provide one bit for programming each defective address bit. In such an approach, the values of defective addresses are first determined. A circuit for each bit is then provided that includes a fuse and a volatile hold circuit, such as a flip-flop, or the like. Upon power-up (when power is initially applied to the semiconductor memory device) the volatile hold circuit will store a “0” or a “1” according to whether the corresponding fuse is opened or not. In this way, only one fuse can be required for each bit of a defective address. Thus, the number fuses can be reduced by half, saving considerable area.
The above-described method, that utilizes one fuse per address bit, differs from the approach shown in Japanese Laid Open Patent Application No. 8-56594 in that the application of power is required to set the defective address values. The application of power in such an “initial setting” operation results in the formation of current paths through the fuse/hold circuit combinations. More particularly, current can flow through a current path and volatile circuit according to whether the corresponding fuse is opened or not. Consequently, a setting operation can draw a substantial amount of transient current. Still further, because the amount of current drawn is proportional to the number of fuses, the more defective addresses there are, the more transient current will be drawn in an initial setting operation.
As noted above, the number of memory cells in a semiconductor device continues to increase each year. Correspondingly, the number of defective memory cells can also increase. In order to maintain high yields, it may be necessary to construct redundancy circuits to address the increasing numbers of defective memory cells. It is thus expected that larger and larger numbers of programming circuits will be needed.
Because the number of programming circuits is expected to increase with higher density memories, the resulting transient current is also expected to increase. At the same time, the power supply requirements for semiconductor memories is not expected to increase, or is expected to increase at a slower rate. This is due to various power conservation techniques, such as dividing a memory into separately activated banks or blocks. Consequently, the power supply specifications may have limited current supplying capabilities, and transient current on power up can become a significant factor in design.
It may be that power supply requirements of a system may be sufficient to meet the transient current requirements resulting from increased numbers of programming circuits. However, such larger current requirements may still present drawbacks in other stages of manufacturing. For example, current requirements can be an important factor when a device is tested prior to being shipped. More particularly, many manufacturing operations can include an accelerated testing step that can detect devices that might fail over time.
Many accelerated testing approaches include mounting a large number of devices on a test board. Such devices can be tested at a lower speed than normal operating speeds. At lower testing speeds, semiconductor devices can draw less instantaneous and/or transient current. Consequently, test boards and corresponding equipment can have limited current supplying capabilities. However, higher density devices having larger numbers of programming circuits may require more current than a typical test board can provide. Consequently, a special, usually more costly, test board must be built to supply the higher start-up current of such devices.
It would be desirable to arrive at some way of providing a semiconductor device having programming circuits for redundancy circuits that does not have as a high a start-up transient current as conventional approaches.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, an address setting circuit may include a first fuse element group in which at least one first defective address may be stored, and a second fuse element group in which at least one second defective address may be stored. A timing circuit can enable current paths through the first and second fuse element groups at substantially different times, distributing transient curre
NEC Corporation
Nguyen Van-Thu
Sako Bradley T.
Walker Darryl G.
LandOfFree
Redundant address setting circuit and semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Redundant address setting circuit and semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundant address setting circuit and semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3332993