Redundant address decoder

Details Redundant address decoder Redundant address decoder

1994-10-07

1996-06-18

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, 36523006, G11C 2900

Patent

active

055285406

ABSTRACT:
A comparator 5 outputs a match signal EQ and a redundancy selection signal with active when an address A4 to A0 is a redundant address in order to select a redundant word line RWL0 or RWL1 for replacing word line WL0 or WL1. A decoder 61 supplies a potential VCC+.alpha. to a drain of an FET 60 when both the match signal EQ and the redundancy selection signal S0 are active. A gate driver 62 supplies a high potential VCC to the gate of the FET 60 for turning ON the FET 60 when the redundancy selection signal S0 is active.

REFERENCES:
patent: 5359559 (1994-10-01), Nomura et al.

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