Redundancy semiconductor memory device with error correction...

Details Redundancy semiconductor memory device with error correction... Redundancy semiconductor memory device with error correction...

2005-07-05

2005-07-05

Tran, Andrew Q. (Department: 2824)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S764000, C714S763000, C365S230030, C365S233100, C365S200000, C365S225700, C365S230080

Reexamination Certificate

active

06915476

ABSTRACT:
A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

REFERENCES:
patent: 6085288 (2000-07-01), Arimilli et al.
patent: 6400292 (2002-06-01), Maeno
patent: 60-201599 (1985-10-01), None
patent: 2002-094368 (2002-03-01), None

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