Redundancy selection apparatus and method for an array

Details Redundancy selection apparatus and method for an array Redundancy selection apparatus and method for an array

1992-06-03

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, G11C 700

Patent

active

053273818

ABSTRACT:
A fused decoder for selecting one or more elements of an array, such as a row of memory, is provided. The corresponding row of memory can be permanently deselected by blowing the fuse of the decoder. Array components such as a redundant row of memory, can be substituted for the deselected component. The decoder includes a gate formed exclusively from NMOS transistors so that the decoder can provide a select signal in response to an address without an PMOS transistor responding to the address- By eliminating PMOS transistors from the gate portion of the decoder, the load presented to the address lines is reduced.

REFERENCES:
patent: 4587638 (1986-05-01), Isobe et al.
patent: 4606013 (1986-08-01), Yoshimoto
patent: 4613959 (1986-09-01), Jiang
patent: 4714839 (1987-12-01), Chung
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4791615 (1988-12-01), Pelley, III
patent: 4829481 (1989-05-01), Johnson
patent: 4839864 (1989-06-01), Fujishima
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 4858192 (1989-08-01), Tatsumi
patent: 4935899 (1990-06-01), Morigami

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