Redundancy scheme for monolithic memories

Details Redundancy scheme for monolithic memories Redundancy scheme for monolithic memories

1995-02-08

1996-06-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

36523001, G11C 1300

Patent

active

055239757

ABSTRACT:
An improved redundancy scheme for monolithic memory devices is disclosed. A memory device (10) has a quadrant array (12) of main memory quadrants (14). Each main memory quadrant (14) includes a number of memory cells arranged in a number of main memory rows (26) and main memory columns (28). A first level of redundancy is provided within each main memory quadrants (14) which has local redundant rows (36) and local redundant columns (38) for replacing defective cells therein. A second level redundancy is provided by redundant memory sections (20) which are used in combination to replace main memory quadrants (14) if necessary. The redundant memory sections (20) are disposed along the edge of the quadrant array (12). A third level of redundancy is provided by redundant section rows (52) and redundant section columns (54) within each redundant memory section (20) to replace defective cells therein.

REFERENCES:
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5402376 (1995-03-01), Horiguchi et al.
patent: 5459690 (1995-10-01), Rieger et al.

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