Redundancy scheme for memory circuits

Details Redundancy scheme for memory circuits Redundancy scheme for memory circuits

1995-08-17

1996-11-05

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Bad bit

365208, G11C 1140

Patent

active

055724710

ABSTRACT:
A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not require disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories.

REFERENCES:
patent: 4464754 (1984-08-01), Stewart et al.
patent: 4577294 (1986-03-01), Brown et al.
patent: 4635232 (1987-01-01), Iwahashi
patent: 4641279 (1987-02-01), Kimura
patent: 4687951 (1987-08-01), McElroy
patent: 5265047 (1993-11-01), Leung
patent: 5450360 (1995-09-01), Sato
IBM Technical Disclosure Bulletin, vol. 34, No. 4A, Sep. 1991, New York US pp. 271-273, XP000210909 "Direct Memory Redundancy".

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