Redundancy scheme for eliminating defects in a memory device

Details Redundancy scheme for eliminating defects in a memory device Redundancy scheme for eliminating defects in a memory device

1990-02-14

1992-06-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, G11C 700

Patent

active

051269732

ABSTRACT:
A redundancy scheme for a memory device, as well as a method for developing a redundancy scheme, resulting in improved repairability for given space constraints. A memory device is formed with a plurality of data blocks having individual input/output paths. Each block comprises an array of memory cells arranged in addressable rows and columns along row lines and column lines. The array is configured in sub-blocks each comprising a plurality of the memory cells. The device includes row address circuitry for selecting a row of the memory cells, column address circuitry for selecting a column of the memory cells and address repair circuitry. The address repair circuitry is configurable to render a first portion of a first of the columns of cells responsive to the address of a portion of a second of the columns of cells. There is also provided a method for eliminating a defect in a memory device having a logical data block formed with addressable rows and columns of memory cells. A defect associated with a first column of cells is eliminated by programming a portion of a second column of cells to be responsive to the addresses of a portion of the cells in the first column.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4604730 (1986-08-01), Yoshida et al.
patent: 4754434 (1988-06-01), Wang et al.

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