Redundancy row/column pretest circuits

Details Redundancy row/column pretest circuits Redundancy row/column pretest circuits

1996-07-15

1997-06-03

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36518908, G11C 2900

Patent

active

056361670

ABSTRACT:
Disclosed are redundancy row/column pretest circuits for a semiconductor memory device. Each of the redundancy row/column pretest circuits comprises a redundancy test pad for supplying a redundancy test signal, and a circuit for generating a normal row or column disable signal in response to the redundancy test signal from the redundancy test pad to disable a normal operation and perform a redundancy operation. Therefore, redundancy row/column cells are operated even under the condition that a redundancy circuit is not programmed, so that faults of the redundancy row/column cells can be tested in the same manner as those of normal cells.

REFERENCES:
patent: 4860260 (1989-08-01), Saito et al.
patent: 4996670 (1991-02-01), Ciraula et al.
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5404331 (1995-04-01), McClure

Affiliated with

Also associated with

Rating

Redundancy row/column pretest circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundancy row/column pretest circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy row/column pretest circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-396770