Redundancy register architecture for soft-error tolerance...

Details Redundancy register architecture for soft-error tolerance... Redundancy register architecture for soft-error tolerance...

2006-10-03

2006-10-03

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S758000

Reexamination Certificate

active

07117428

ABSTRACT:
A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

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