Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-02-18
2001-06-19
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S189020
Reexamination Certificate
active
06249465
ABSTRACT:
BACKGROUND
Random access memory (“RAM”) is commonly implemented within computer systems of the prior art. Computer systems may employ a multi-level hierarchy of memory, with relatively fast, expensive but limited-capacity memory at the highest level of the hierarchy and proceeding to relatively slower, lower cost but higher-capacity memory at the lowest level of the hierarchy. The hierarchy may include a small fast memory called a cache, either physically integrated within a processor or mounted physically close to the processor for speed. The computer system may employ separate instruction caches (“I-caches”) and data caches (“D-caches”). In addition, the computer system may use multiple levels of caches. The use of a cache is generally transparent to a computer program at the instruction level and can thus be added to a computer architecture without changing the instruction set or requiring modification to existing programs. Generally, RAM may be implemented within any such level of a multi-level hierarchy of memory utilized for a computer system.
Various RAM chips have been developed in the prior art to allow data to be moved in and out of memory quickly, to avoid errors, and to make collections of RAM chips smaller. The most common types of RAM include dynamic random access memory (DRAM), Extended Data Out random access memory (EDO RAM), video random access memory (VRAM), static random access memory (SRAM), synchronous DRAM (SDRAM), single in-line memory modules (SIMM), dual in-line memory modules (DIMM), and error-correcting code (ECC) chips. It is common in manufacturing (or “fabricating”) a RAM chip that a defect may occur within a portion of the chip. That is, a portion of the RAM may not allow for the proper storage and/or retrieval of data. Accordingly, techniques have been developed in the prior art for detecting and correcting such defects. Generally, redundancy is desired in a chip or system with a large number of memory or circuit blocks where a defective block could be mapped to a non-defective block to improve the manufacturing yield and/or to keep a system operating properly. Typically, RAM memory is implemented in such a redundant system, and therefore the following description of the prior art focuses primarily on RAM memory implementations. However, it should be recognized that various other types of memory may be implemented with redundancy as well.
A common technique that is utilized in the prior art to correct defects detected in RAM chips is to provide redundant sub-blocks of memory within a RAM chip, which can be used to effectively replace a defective sub-block of memory within the chip. Turning to
FIG. 1
, an exemplary overview of implementing redundant sub-blocks within a RAM structure is shown. As shown, a very large RAM block (or RAM structure)
300
may be implemented within a chip. If a defect is present in the RAM block
300
, it is desirable to be capable of repairing it to improve the yield of the die, and once it is determined that RAM
300
either has no defects or all of its defects have been repaired, to then ship the chip or system that includes RAM
300
to a customer. Repairing a defective RAM block
300
may be accomplished by providing a group of redundant sub-blocks, such as sub-blocks
310
,
312
, and
314
, which may be used to replace a defective sub-block within RAM block
300
. Accordingly, the term “repair” as used herein should not be read narrowly to mean physically repairing a defective sub-block, but should instead be read more broadly to encompass avoiding a defective sub-block. Ideally, it would be desirable to be capable of repairing any defective location in the RAM block
300
with any one of the redundant sub-blocks (e.g., any one of sub-blocks
310
,
312
,
314
, etc.). However, a problem arises when shipping data (i.e., “memory data”) from a defective sub-block within RAM block
300
to a redundant sub-block that is physically located at a relatively far distance away. That is, when a redundant sub-block is located relatively far away from a defective sub-block, the latency involved in transporting data such a long distance has a negative impact on the system's performance.
For example, suppose a defect occurs within sub-block
350
of RAM
300
, which is physically located a relatively far distance away from the redundant sub-blocks (
310
,
312
,
314
, etc.). To repair sub-block
350
, write data would have to be shipped from the port of sub-block
350
all the way over to a redundant sub-block, such as redundant sub-block
310
, and read data would have to be shipped out from the redundant sub-block
310
to the port of sub-block
350
so it can be driven to its desired destination on the chip. The additional latency (i.e., wiring delay) resulting from shipping data such a long distance can have a large, negative impact on the performance of the system. That is, the additional latency resulting from shipping data a relatively long distance from a defective location to a redundant sub-block increases the amount of time required to access data within the redundant sub-block, thereby slowing the operating speed of the system.
Turning to
FIG. 2
, a design of the prior art that utilizes redundant sub-blocks to repair a RAM block
300
is illustrated. In the solution of
FIG. 2
, a large RAM block
300
is partitioned into smaller segments (or “banks”), such as segments
302
,
304
,
306
and
308
. For each one of the segments
302
,
304
,
306
, and
308
, a redundant sub-block is assigned thereto. More specifically, redundant sub-block
310
is associated with segment
302
, redundant sub-block
312
is associated with segment
304
, redundant sub-block
314
is associated with segment
306
, and redundant sub-block
316
is associated with segment
308
. Accordingly, any defect in segment
302
can effectively be repaired with its redundant sub-block
310
. Similarly, any defects within any of the other segments may be repaired using their respective associated redundant sub-blocks.
To further illustrate the operation of the prior art RAM design shown in
FIG. 2
, suppose that sub-block (or “sub-array”)
321
within segment
302
is defective. Data is shifted from the nearest sub-block to the right of sub-block
321
to repair sub-block
321
. That is, sub-block
320
is routed out to the input/output port (I/O port) of sub-block
321
through a MUX (not shown). Each of the remaining blocks to the right of sub-block
320
(i.e., sub-blocks
319
and
318
of
FIG. 2
) is shifted in a similar manner, and finally redundant sub-block
310
is shifted to provide the data for sub-block
318
. Shifting of the nearest neighbor in this manner results in a relatively short routing length because data is only routed to a sub-block's nearest neighbor. Therefore, this prior art RAM design may be implemented to provide a high yield of a die by effectively allowing a defective RAM to be repaired.
It should be recognized that the exact manner in which the RAM block
300
is partitioned may vary. Typically, the number of segments in which a RAM block is partitioned is dependent on the number of functional units implemented for the RAM (e.g., the number of data cache units, tag cache units, etc.). More specifically, it is typically desirable to have the RAM segmented in a manner that allows for each functional unit to be repaired separately. For instance, the large RAM block
300
may be partitioned into six D-cache data segments, two I-cache data segments, two D-cache tag segments, and two I-cache tag segments. It should be recognized that any number of segments may be implemented in this manner. Typically, for a larger size RAM block
300
, a greater number of segments are desirable in order to allow a high yield of the die. It should also be understood that each sub-block of a segment (e.g., sub-block
321
,
320
,
319
,
318
,
310
, etc.) may actually comprise a group or “array” of memory cells. Thus, each sub-block may comprise X number of rows of memory cells by Y number of columns of memory cells. Accord
Brauch Jeffery C
Fleischman Jay
Weiss Donald R
Hewlett--Packard Company
Hoang Huan
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