Redundancy programming circuit and system for semiconductor memo

Details Redundancy programming circuit and system for semiconductor memo Redundancy programming circuit and system for semiconductor memo

1997-06-19

1999-04-27

Mai, Son

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

058986260

ABSTRACT:
Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.

REFERENCES:
patent: 5579266 (1996-11-01), Tahara
patent: 5657280 (1997-08-01), Shin et al.
patent: 5671185 (1997-09-01), Chen et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5696723 (1997-12-01), Tukahara

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