Redundancy multiplexer for a semiconductor memory configuration

Details Redundancy multiplexer for a semiconductor memory configuration Redundancy multiplexer for a semiconductor memory configuration

2001-02-26

2002-05-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230020

Reexamination Certificate

active

06385102

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor and semiconductor memory fields. More specifically, the present invention relates to a redundancy multiplexer for a semiconductor memory configuration for replacing a faulty bit line with a redundant bit line. A control signal is generated in a decoder from information, stored in fuses, about which bit line is to be replaced, and in which two redundancy areas containing the redundant bit line can be selected by the control signal on both sides of a central bus.
FIG. 3
of the drawings shows the design of a conventional redundancy multiplexer for a semiconductor memory configuration. On both sides of a central bus or central area
1
, there is an input/output unit (I/O)
2
into which information about which bit line is faulty and needs to be replaced with a redundant bit line is input. In this context, it is naturally possible to replace as many bit lines with redundant bit lines as there are redundant bit lines in total. This information about faulty bit lines is stored in fuses (FUSES)
3
. This means that these fuses contain coded fuse information CFI which indicates which bit lines are faulty and need to be replaced with redundant bit lines. We assume here that this coded fuse information CFI on each side of the central bus
1
is output directly, or via control units
6
,
7
used during reading or writing, to a redundancy multiplexer (RMUX)
8
,
9
via an appropriate fuse bus
4
(indicated schematically by a dotted line) via a buffer and decoder
5
which supplies decoded fuse information FI. By way of example, the fuses
3
situated on the right of the central bus
1
in
FIG. 3
thus transmit the coded fuse information CFI via the buffer and decoder
5
, which produces the decoded fuse information FI therefrom, to the control unit
6
, and the latter distributes it over the entire interface width of the redundancy multiplexer
9
using sense amplifiers (SSA)
10
before the associated redundant bit line in an area
11
next to the memory cell array
13
is driven.
Such a procedure for selecting redundant bit lines presents no problems as long as the interface width between the redundancy multiplexers
8
,
9
and the sense amplifiers
10
and/or the memory cell array
13
is relatively narrow. With increasing interface width, such as in the case of a 128 bit eDRAM, the relatively large interface width builds up time delays, which present a serious problem: as shown schematically in
FIG. 3
, the control signals for driving each redundant bit line have to pass through the entire width of the interface, which means that the fuse information CFI or FI has to propagate over a maximum of ¾ of the interface width. By way of example, the fuse information CFI or FI needs to pass from the fuse area
3
situated on the left of the central bus
1
in
FIG. 3
(cf. dotted line
4
) to the control unit
7
and then propagate from there to the right-hand or left-hand edge of the redundancy multiplexer
9
, until the sense amplifier
10
associated with the redundant bit line in area
11
has been found.
This time delay is ultimately caused by the redundant bit lines in area
11
for the redundancy multiplexer
9
and in area
12
for the redundancy multiplexer
8
being driven via the entire width of the interface on both sides of the central bus
1
.
In order to maintain a maximum number of repair opportunities for faulty bit lines using redundant bit lines, the normal arrangement inevitably involves long delay times caused by the control signals propagating over ¾ of the interface width.
FIG. 4
illustrates the details of the layout of the existing redundancy multiplexer
8
or
9
of FIG.
3
: starting from a decoder
5
which is arranged on both sides of the central bus
1
and receives information from five fuses
3
(four fuses for address information “Coded Fused address” and one fuse for “Fused Enable”), 16 switch signals are respectively supplied on both sides of the central bus
1
in order to drive 16 switches
14
in the redundancy multiplexer
8
(for the decoder
5
on the right in
FIG. 4
) and 16 switches
14
in the redundancy multiplexer
9
(for the decoder
5
on the left in FIG.
4
).
On the basis of these switch signals, the data input into the switches
14
(“Data in”) are passed on by the switches
14
in the redundancy multiplexers
8
,
9
(“Data out”), in order thus to drive any redundant bit lines, for example in the area of the central bus
1
, as indicated schematically in
FIG. 4
by “RED”.
This prior art layout may be termed unilateral, since no distinction is drawn between the two sides of the central bus
1
for the redundancy multiplexers
8
,
9
, and the redundancy multiplexers
8
,
9
are “unilateral” for the central bus
1
and hence also for the entire interface width.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a redundancy multiplexer for a semiconductor memory which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which prevents the delay times caused by the unilateral structure when the switching signals are propagated and is thus distinguished by shortened propagation times for these switching signals.
With the above and other objects in view there is provided, in accordance with the invention, a redundancy multiplexer for a semiconductor memory configuration for replacing a faulty bit line with a redundant bit line, which comprises:
a decoder having an input receiving information, stored in fuses, concerning a bit line to be replaced, and generating therefrom a control signal;
a first redundancy area containing first redundant bit lines in a first area on a first side of a central bus;
a second redundancy area containing second redundant bit lines in a second area on a second side of the central bus opposite the first side;
the first and second redundancy areas being selectable by the control signal;
the decoder transmitting the control signals to the first and second redundancy areas bilaterally, such that the control signals each propagate only on one side of the central bus, and that the parts of the first and second redundancy areas situated on the first or second side of the central bus receive, via the control signals, only the decoded fuse information for redundant bit lines in the first or second area, and such that a propagation time of the control signal depends on a signal path via half of the part of the first or second redundancy area situated on the one side of the central bus defining one quarter of an interface width of the redundancy multiplexer.
The invention achieves this object for a redundancy multiplexer of the type mentioned initially by virtue of the fact that, in each case, the decoder supplies the switching or control signal only to zones of the two redundancy areas which are situated on one side of the central bus.
In accordance with an added feature of the invention, each part of the first and second redundancy areas is configured to be utilized for connecting at least one redundant bit line for each faulty bit line.
The redundancy multiplexer according to the invention thus provides a bilateral design. The fuse information decoded in the decoder is evaluated only in control or switching signals on one side of the central bus, which makes it possible to reduce the distance over which these signals have to be propagated to ¼ of the interface width. In other words, the signal propagation time is reduced by a factor of 3. This means that fuse information for the decoder and the switching or control signals supplied by the decoder remain on one or other side of the central bus. However, since in all the information input into the input/output unit is coded in the fuses and this information is decoded in the buffer and decoder, a faulty bit line in one half of the arrangement, that is to say on one side of the central bus, can be replaced with a redundant bit line on the other side of this central bus

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