Redundancy method and software to provide improved...

Details Redundancy method and software to provide improved... Redundancy method and software to provide improved...

2008-03-18

2008-03-18

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S010000

Reexamination Certificate

active

11476239

ABSTRACT:
A method and computer readable medium for implementing redundancy on a programmable logic device with improved interconnect efficiency. The method and medium includes: determining if a first wire segment of a first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; reserving a next segment in the first channel if the first wire segment of the first wire channel requires a programmed connection to a resource in the row furthest from the buffer driving the first wire segment and spanned by the first wire segment; and assuming a maximum delay path including the programmable signal propagation delay of the reserved next segment and a stitching element coupled between the first segment and the reserved next segment of the first channel.

REFERENCES:
patent: 6201404 (2001-03-01), Reddy et al.
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6826741 (2004-11-01), Johnson et al.
patent: 2003/0072185 (2003-04-01), Lane et al.
patent: 2005/0264318 (2005-12-01), Chan

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