Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-04-17
1998-09-22
Fears, Terrence W.
Static information storage and retrieval
Read/write circuit
Bad bit
36518901, G11C 1300
Patent
active
058124675
ABSTRACT:
A redundancy memory register for storing defective addresses of defective memory elements in a memory device includes a plurality of memory units each one storing a respective defective address bit and comparing the defective address bit stored therein with a respective current address bit of a current address supplied to the memory device. The register includes a first group of memory units and a second group of memory units storing a first defective address, and a third group of memory units storing, together with the first group, a second defective address which has an address part in common with the first defective address. The first and second group of memory units supply first redundancy selection means for selecting a first redundancy memory element when the current address coincides with the first defective address. The first and third group of memory units supply second redundancy selection means for selecting a second redundancy memory element when the current address coincides with the second defective address. The register comprises first address configuration detection means for detecting if the current address coincides with a default configuration stored in the first and second group of memory units and for correspondingly deactivating the first and second redundancy selection means, and second address configuration detection means for detecting if the current address coincides with a default configuration stored in the third group of memory units and for consequently deactivating the second redundancy selection means.
REFERENCES:
patent: 5659509 (1997-08-01), Golla et al.
patent: 5687125 (1997-11-01), Kikucni
European Search Report from European Patent Application 96830215.8, filed Apr. 18, 1996.
Fears Terrence W.
SGS--Thomson Microelectronics S.r.l.
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