Redundancy memory circuit

Details Redundancy memory circuit Redundancy memory circuit

2001-06-27

2002-08-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S063000

Reexamination Certificate

active

06442083

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a redundancy memory circuit, and more particularly to a redundancy memory circuit for writing address data of a defective memory area into nonvolatile memory capable of electrically writing and reading, and reading out this address data and making repairs on the defective memory area (relief of defective memory).
A redundancy memory circuit has been used in many memory circuits such as DRAM, EEPROM for the purpose of repairing defective bits of a bulk memory device. In memory (EEPROM) capable of electrically writing, reading and erasing, repairs were electrically made by writing and reading a redundancy address using a part of the EEPROM.
FIG. 4
is a schematic diagram showing a configuration of a conventional redundancy memory circuit applied to EEPROM. A memory mat
50
including plural EEPROM memories capable of electrically writing, reading and erasing is constructed of a main memory area
51
, a redundancy memory area
52
for replacing a defective memory area occurring in the main memory area, and an inforow memory area
53
for storing various manufacturing information. Here, the redundancy memory area
52
and the inforow memory area
53
are provided in address space separate from the main memory area
51
.
Also, numeral
54
denotes a first address decoder for accessing the main memory area
51
based on address data, and numeral
55
denotes a second address decoder for accessing the redundancy memory area
52
based on redundancy address data. Then, numeral
56
denotes redundancy address memory for writing and storing address data of a memory area in which a defect occurs, and was provided as dedicated memory in an area physically distant from the memory mat
50
described above.
Summarizing operations of the redundancy memory circuit with the configuration described above, address data inputted from the outside is compared with address data of a defective memory area stored in the redundancy address memory
56
by a comparison circuit (not shown) and when both the data match, a word line selection output of the first address decoder
54
is inhibited (access to the defective memory area is inhibited) At the same time, a word line selection output of the second address decoder
55
became enabled and the redundancy memory area
52
is accessed and thereby, the defective memory area is repaired.
However, the redundancy address memory
56
was provided in an area physically distant from the memory mat
50
on a chip, so that there was the need to dedicatedly provide an analog control circuit such as an analog bias circuit used in data writing and there was a problem that a circuit scale becomes large.
Also, in the case of desiring to change a size of the redundancy memory area in some type of machine, a size of the redundancy address memory
56
must also be changed accordingly, but a change in a layout of a chip is as difficult since the redundancy address memory
56
is provided in an area physically distant from the memory mat
50
. For example, in the case of changing a size of the redundancy address memory
56
to ½ (for example, a change from support for 4 sectors to support for 2 sectors), there is a problem that a useless free area occurs and a chip size becomes large.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to eliminate the need to dedicatedly provide a control circuit such as an analog bias circuit and reduce a circuit scale by forming redundancy address memory within the same memory mat as a main memory area or facilitate expansion and reduction of the redundancy address memory to reduce a chip size.
A redundancy memory circuit of the invention is characterized by comprising a main memory area including of plural nonvolatile memories capable of electrically writing and reading, means for writing redundancy address data corresponding to a defective memory area occurring in the main memory area in to a redundancy address memory area provided within the same memory mat as the main memory area, and means for reading the redundancy address data, characterized in that the defective memory area is repaired on the basis of the redundancy address data read from the redundancy address memory area.
In accordance with such means, the redundancy address memory area is formed within the same memory mat as the main memory area, so that the need to dedicatedly provide a dedicated EEPROM cell for storing redundancy address data and an analog control circuit for writing the redundancy address data into this EEPROM cell is eliminated and a chip size can be reduced.
Also, a size of the redundancy address memory area can be changed easily, so that memory design according to specifications of a type of machine can be performed in a short time while the chip size can be reduced.


REFERENCES:
patent: 5983358 (1999-11-01), Horiguchi et al.
patent: 6201728 (2002-03-01), Narui et al.

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