Redundancy mapping in a multichip semiconductor package

Details Redundancy mapping in a multichip semiconductor package Redundancy mapping in a multichip semiconductor package

2001-06-12

2003-03-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C365S200000

Reexamination Certificate

active

06531339

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to multichip semiconductor packages and in particular the present invention relates to redundancy mapping in multichip semiconductor packages.
BACKGROUND OF THE INVENTION
As the number of electronic elements contained on semiconductor integrated circuits continues to increase, the problems of reducing and eliminating defects in the elements becomes more difficult. To achieve higher population capacities, circuit designs strive to reduce the size of the individual elements to maximize available die real estate. The reduced size, however, makes these elements increasingly susceptible to defects caused by material impurities during fabrication. These defects can be identified upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective circuits is economically undesirable, particularly if only a small number of elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option, however. To reduce the amount of semiconductor scrap, therefore, redundant elements are provided on the circuit. If a primary element is determined to be defective, a redundant element can be substituted for the defective element. Substantial reductions in scrap can be achieved by using redundant elements.
One way to reduce semiconductor scrap is to provide redundant elements on the integrated circuits. If a primary element is defective a redundant element can be substituted for that defective element. One example of an integrated circuit device which uses redundant elements is electronic memory. Typical memory circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. By providing redundant elements, defective memory cells or columns can be replaced. Because the individual primary memory cells of a memory are separately addressable, replacing a defective cell typically comprises opening fuse-type circuits to ‘program’ a redundant cell to respond to the address of the defective primary cell. This process is very effective for permanently replacing defective primary memory cells. For example,
FIG. 1
illustrates a typical memory circuit where primary memory columns (PRIME
0
to PRIME
i
) are selectively connected to data communication lines (DATA
0
and DATA
i
). When a primary column is addressed via external address lines, the appropriate select signal (SEL
0
to SEL
i
) is activated. If a primary column is determined to be defective, its select signal is forced to a permanent inactive state, and a compare circuit is programmed to activate an appropriate redundant select signal (RSEL
0
to RSEL
i
). This programming is typically performed using fusible circuits. When an address of the defective column is provided on the address lines, the compare circuit responds by activating the redundant select signal to couple the redundant column to the appropriate data communication line.
Because the individual primary elements of a memory are separately addressable, replacing a defective element typically comprises selecting a bank of switch circuits, each switch circuit typically being an antifuse or a fuse such that the bank is known as an antifuse bank or a fuse bank, respectively, to ‘program’ a redundant element to respond to the address of the defective element, and then enabling the redundant element by programming an enable antifuse. This process is very effective for permanently replacing defective primary elements. A problem can occur, however, when an integrated circuit is fabricated with more defects than available redundant circuits. As such, the circuit will become scrap.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a semiconductor device which can be repaired to correct defects which out number available redundant circuitry on the same semiconductor die.
SUMMARY OF THE INVENTION
The above mentioned problems with semiconductor devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A multichip integrated circuit package is described which provides internal redundancy between chips.
In particular, the present invention describes a multichip integrated circuit package is described which comprises a plurality of semiconductor chips integrally formed on a unitary substrate. Each of the plurality of semiconductor chips comprises redundant circuitry adapted to selectively replace primary circuitry. A plurality of electrical interconnects are provided to couple the redundant circuitry from a first one of the plurality of semiconductor chips to a second one of the plurality of semiconductor chips.
In another embodiment, a multichip integrated circuit package comprises a plurality of integrated circuit memory chips integrally formed on a unitary substrate. Each of the plurality of integrated circuit memory chips comprises an array of primary memory cells and redundant memory cells. A plurality of electrical interconnects couple the redundant memory cells from a first one of the integrated circuit memory chips to a second one of the integrated circuit memory chips. Control circuitry is provided to select the redundant circuitry from the first one of the plurality of integrated circuit memory chips.
A method of making a multichip integrated circuit package is described. The method comprises integrally forming a plurality of isolated integrated circuit chips on a unitary substrate, and electrically connecting the plurality of isolated integrated circuit chips using interconnects to couple redundant circuitry from a first one of the plurality of integrated circuit chips to a second one of the plurality of integrated circuit chips.


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