Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-02-15
2005-02-15
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S145000
Reexamination Certificate
active
06856560
ABSTRACT:
An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.
REFERENCES:
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5898615 (1999-04-01), Chida
patent: 5903492 (1999-05-01), Takashima
patent: 6317355 (2001-11-01), Kang
patent: 6493251 (2002-12-01), Hoya et al.
patent: 6496428 (2002-12-01), Ohno et al.
patent: 6525974 (2003-02-01), Neuhold et al.
Joachim Hans-Oliver
Rehm Norbert
Roehr Thomas
Wohlfahrt Joerg W.
Horizon IP Pte Ltd
Infineon Technologies Aktiengesellschaft
Nguyen Tan T.
LandOfFree
Redundancy in series grouped memory architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Redundancy in series grouped memory architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy in series grouped memory architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3456981