Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-10-17
2006-10-17
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S201000
Reexamination Certificate
active
07123527
ABSTRACT:
A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.
REFERENCES:
patent: 6034903 (2000-03-01), Ichikawa
patent: 6111798 (2000-08-01), Lee
patent: 6205050 (2001-03-01), Tamaki
patent: 6400620 (2002-06-01), Yoo
patent: 6741499 (2004-05-01), Imamiya et al.
patent: 6845043 (2005-01-01), Dono
patent: 2004/0240249 (2004-12-01), Kuzuno et al.
patent: 4-238199 (1992-08-01), None
patent: 2001-307497 (2001-11-01), None
U.S. Appl. No. 11/130,141, filed May 17, 2005, Takeda, et al.
Kubota Masaya
Kuzuno Naokazu
Maruyama Kimio
Oikawa Kiyoharu
Watanabe Yasuhiro
Kabushiki Kaisha Toshiba
Le Thong Q.
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