Redundancy for low remanence memory cells

Details Redundancy for low remanence memory cells Redundancy for low remanence memory cells

1999-05-27

2000-07-18

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

060916508

ABSTRACT:
A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.

REFERENCES:
patent: 4473895 (1984-09-01), Tatematsu
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5563832 (1996-10-01), Kagami
patent: 5889713 (1999-03-01), Chan et al.
patent: 6011734 (2000-01-01), Pappert
Hiroki Koike, et al. "A 30ns 64Mb DRAM with Built-in Self-Test and Repair Function", IEEE International Solid State Circuits Conference, vol. 35, Feb. 1, 1992, p. 150-151.
French Search Report dated Feb. 8, 1999 with annex on French Application No. 9806970.

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