Redundancy decoder

Details Redundancy decoder Redundancy decoder

1992-01-31

1995-11-28

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523002, 36523006, G11C 700, G11C 2900

Patent

active

054714265

ABSTRACT:
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of address fuses for storing the column address responsive to which its associated redundant column is to be selected, and which are in series with pass gates which are turned on when redundancy is enabled, and turned off otherwise. This arrangement of address fuses and pass gates reduces and balances the loading of the decoder on the address lines, may be implemented with fewer transistors and thus in reduced chip area relative to conventional decoders, and also reduces the propagation delay through the decoder. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

REFERENCES:
patent: 4573146 (1986-02-01), Graham et al.
patent: 4714839 (1987-12-01), Chung
patent: 4734889 (1988-03-01), Mashiko et al.
patent: 4829480 (1989-05-01), Seo
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 5058059 (1991-10-01), Matsuo et al.
Hardee, et al., "A Fault-Tolerant 20 ns/375 mW 16K.times.1 NMOS Static Ram", J. Solid State Circuits, vol. SC-16, No. 5 (IEEE, 1981), pp. 435-443.
Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, 1984), pp. 545-551.
Sakurai, et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line", IEEE J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, Oct. 1984) pp. 578-585.

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