Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-12-29
1998-08-04
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Bad bit
36518901, 36518902, 365203, 36518908, 365190, G11C 700, G11C 1300
Patent
active
057904626
ABSTRACT:
An integrated circuit memory structure is disclosed where the read and write buses (true and complement) are coupled to redundant input/output select circuits through permanently programmable selection element that can disconnect the read and write busses from the redundant input/output select circuit.
REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4573146 (1986-02-01), Graham et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4689494 (1987-08-01), Chen et al.
patent: 4714839 (1987-12-01), Chung
patent: 4734889 (1988-03-01), Mashiko et al.
patent: 4791615 (1988-12-01), Pelley, III et al.
patent: 4829480 (1989-05-01), Seo
patent: 4833652 (1989-05-01), Isobe et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4985866 (1991-01-01), Nakaizuri
patent: 5034925 (1991-07-01), Kato
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5107464 (1992-04-01), Sahara et al.
patent: 5124948 (1992-06-01), Takazawa et al.
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5177743 (1993-01-01), Shinoda et al.
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5262994 (1993-11-01), McClure
patent: 5265054 (1993-11-01), McClure
patent: 5281868 (1994-01-01), Morgan
patent: 5295102 (1994-03-01), McClure
patent: 5297090 (1994-03-01), McClure
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5305268 (1994-04-01), McClure
patent: 5307316 (1994-04-01), Takemae
patent: 5311471 (1994-05-01), Ota
patent: 5337278 (1994-08-01), Cho
patent: 5355340 (1994-10-01), Coker et al.
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5455798 (1995-10-01), McClure
patent: 5471426 (1995-11-01), McClure
patent: 5495446 (1996-02-01), Teel et al.
U.S. application No. 08/438,349, McClure et al., filed May 10, 1995.
U.S. application No. 08/438,903, McClure et al., filed May 10, 1995.
U.S. application No. 08/509,351, Lysinger, filed Jul. 31, 1995.
Childs, et al., "An 18 ns 4K .times. 4 CMOS SRAM," J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, 1984), pp. 545-551.
Sakurai, et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line," IEEE J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, Oct. 1984), pp. 578-585.
Nishimura, et al., "A Redundancy Test-Time Reduction Technique in 1Mbit DRAM with a Multibit Test Mode," IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 43-49.
Kayano, et al., "25-ns 256K .times. 1/64K .times. 4 CMOS SRAM's," IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 686-690.
Hardee, et al., "A Fault-Tolerant 20 ns/375 mW 16K .times. 1 NMOS Static Ram," J. Solid State Circuits, vol. SC-16, No. 5 (IEEE, 1981), pp. 435-443 .
Galanthay Theodore E.
Jorgenson Lisa K.
Lager Irena
Nguyen Viet Q.
SGS-Thomson Microelectronics Inc.
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