Redundancy circuitry layout for a semiconductor memory device

Details Redundancy circuitry layout for a semiconductor memory device Redundancy circuitry layout for a semiconductor memory device

1995-03-29

1996-09-24

Dinh, Son

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, 371 102, G11C 700

Patent

active

055597432

ABSTRACT:
Redundancy circuitry layout for a semiconductor memory device comprises an array of programmable non-volatile memory elements for storing the addresses of detective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines. The redundancy circuitry layout is divided into identical layout strips which are perpendicular to the array of memory elements and which each comprise first and a second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one programmable non-volatile memory register of a first plurality for the selection or redundancy bit lines and being crossed by a column address signal bus running parallel to the array or memory elements, the second strip side containing one programmable non-volatile memory register of a second plurality for the selection or redundancy word lines and being crossed by a row address signal bus running parallel to the array of memory elements.

REFERENCES:
patent: 4811306 (1989-03-01), Boning et al.
patent: 5231604 (1993-07-01), Watanabe
patent: 5255227 (1993-10-01), Haeffele
patent: 5459690 (1995-10-01), Rieger et al.

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