Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2000-12-13
2002-08-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000
Reexamination Certificate
active
06430100
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a redundancy circuitry used in a memory for repairing defects after packaging; and, more particularly, to a redundancy circuitry, which is capable of repairing one or more defects in a packaged memory having register, thereby increasing yields and reducing fabrication costs.
DESCRIPTION OF THE PRIOR ART
There have been lots of efforts to increase operation speed of memory for a long time. One of the kinds is a memory having registers.
Memories like static dynamic random access memory SDRAM store data directly into their main memory cell and retrieve it from the main memory cell. The memories having registers, however, use registers working as a kind of buffers to temporarily store the data.
Generally, in memories having registers like a virtual channel memory (VCM) defected cells are replaced by redundancy cells in a wafer level by laser repair device before being packaged. However, there is no method known to replace the defected cells with redundancy cells after packaging because laser repair device cannot be used at a package level.
A virtual channel memory has a register called channel. Data can be written to or read from the channel instead of main memory cell and thus a high-speed operation is possible. There are typical operations such as pre-fetch, read, write and restore operations in VCM. The pre-fetch is an operation for transferring data from the memory cell to the channel, the read operation is to read data from the channel, the write operation is to write data to the channel, and the restore is an operation for transferring the data from the channel to the memory cell.
According to prior art, an active operation of a row path is occurred before a read operation of column path on pre-fetch and read operations. On the other hand, write operation of column path is occurred before active (restore) operation of row path on write and restore operations. Thus it was very difficult, if not impossible, to implement redundancy circuitry employing antifuse, thereby decreasing yields and increasing fabrication costs.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide to a redundancy circuitry, which is capable of repairing one or more defects in a packaged memory having register, thereby increasing yield and reducing fabrication costs.
In accordance with an aspect of the present invention, there is provided a redundancy circuitry used in the memory device, comprising: an anticell means for storing data to be replaced; a temporary anticell means for storing said data temporarily; a row antifuse means composed of antifuse and anti enable fuse corresponding to a row address used to program the antifuse for replacing defected cells with redundant cells in the memory; a column antifuse means composed of antifuse and anti enable fuse corresponding to a column address used to program the antifuse for replacing the defected cells with the redundant cells in the memory; an antifuse control means for controlling the programming of the antifuse in the row and column antifuse means based on said row and column addresses; a voltage supplier for supplying a voltage to program said antifuse in said row and column antifuse by said antifuse control means; a row comparator for comparing programmed said row antifuse from the row antifuse means and an external input address, thereby generating a first comparison signal; a column comparator for comparing programmed said column antifuse from the column antifuse means and the external input address, thereby generating a first comparison signal; an anti-control means for controlling to provide data from said anticell on a read operation and to temporarily store the external data to said temporary anticell on a write operation based on said first and second comparison signals from said row and column comparators; a restore control means for, based on the row address on a restore operation, transferring the external data identical to the programmed fuse address to said anticell, wherein said external data is stored temporarily in said temporary anticell by a control signal from said anti-control means and said first comparison signal from said row comparator; a channel selection memory for storing the channel address for pre-fetch and restore operations provided during read and write operations.
REFERENCES:
patent: 5920515 (1999-07-01), Shalk et al.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co., LTD
Le Vu A.
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