Electronic digital logic circuitry – Reliability – Redundant
Patent
1999-11-03
2000-07-18
Tokar, Michael
Electronic digital logic circuitry
Reliability
Redundant
326 38, 326 41, H03K 19003, H03K 19173, H03K 19177
Patent
active
060912588
ABSTRACT:
Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
REFERENCES:
patent: Re33521 (1991-01-01), Mori et al.
patent: 3566153 (1971-02-01), Spencer, Jr. et al.
patent: 3805039 (1974-04-01), Stiffler
patent: 3995261 (1976-11-01), Goldberg
patent: 4020469 (1977-04-01), Manning
patent: 4051354 (1977-09-01), Choate
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4380811 (1983-04-01), Gotze et al.
patent: 4538247 (1985-08-01), Venkateswaran
patent: 4551814 (1985-11-01), Moore et al.
patent: 4566102 (1986-01-01), Hefner
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4641285 (1987-02-01), Sasaki et al.
patent: 4677318 (1987-06-01), Veenstra
patent: 4691301 (1987-09-01), Anderson
patent: 4700187 (1987-10-01), Furtek
patent: 4703206 (1987-10-01), Cavlan
patent: 4706216 (1987-11-01), Carter
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4722084 (1988-01-01), Morton
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4798976 (1989-01-01), Curtin et al.
patent: 4800302 (1989-01-01), Marum
patent: 4829198 (1989-05-01), Maley et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4920497 (1990-04-01), Upadhyaya et al.
patent: 4928022 (1990-05-01), Marum
patent: 5019736 (1991-05-01), Furtek
patent: 5045720 (1991-09-01), Bae
patent: 5121006 (1992-06-01), Pedersen
patent: 5163023 (1992-11-01), Ferris et al.
patent: 5187393 (1993-02-01), El Gamal et al.
patent: 5204836 (1993-04-01), Reed
patent: 5220214 (1993-06-01), Pedersen
patent: 5237219 (1993-08-01), Cliff
patent: 5255227 (1993-10-01), Haeffele
patent: 5255228 (1993-10-01), Hatta et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5325334 (1994-06-01), Roh et al.
patent: 5369314 (1994-11-01), Patel et al.
patent: 5426379 (1995-06-01), Trimberger et al.
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5459342 (1995-10-01), Nogami et al.
patent: 5471427 (1995-11-01), Murakami et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5508636 (1996-04-01), Mange et al.
patent: 5592102 (1997-01-01), Lane et al.
patent: 5670895 (1997-09-01), Kazarian et al.
"A Survey of Microcellular Research", R.C. Minnick, Journal of the Association of Computing Machinery, vol. 14, No. 2, pp. 203-41, Apr. 1967.
"Programmable Logic Arrays--Cheaper by the Millions," S.E. Wahlstrom, Electronics, Dec. 1967, pp. 90-95.
"Recent Developments in Switching Theory", A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422.
"Memories and Redundancy Techniques", K. Kokkonen et al., Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 80-1, Feb., 1981.
"Cost-Effective Yield Improvement in Fault-Tolerant VLSI Memory", J. Binders et al., Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 82-3, Feb., 1981.
"A 100ns 64K Dynamic RAM using Redundancy Techniques", S. Eaton et al., Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 84-5, Feb., 1981.
"Introducing Redundancy In Field Programmable Gate Arrays", F. Hatori et al., Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pp. 7.1.1--7.1.4, May 1993.
"On the Design of a Redundant Programmable Logic Array (RPLA)", C.-L. Wey et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 1, Feb. 1987, pp. 114-17.
Preliminary Data booklet for Altera 32 Macrocell High Density Max EPLD EPM5032, 1988, Altera Corporation.
"Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits", Altera Corporation.
"Laser Correcting Defects Transparent Routing for Larger Area FPGA's", G.H. Chapman and B. Dufort, FGPA '97-ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 1997, pp. 17-23.
Cliff Richard G.
Lee Andy L.
McClintock Cameron
Altera Corporation
Cho James A.
Jackson Robert R.
Tokar Michael
Treyz G. Victor
LandOfFree
Redundancy circuitry for logic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Redundancy circuitry for logic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy circuitry for logic circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2040378