Redundancy circuit with memorization of output contact pad posit

Details Redundancy circuit with memorization of output contact pad posit Redundancy circuit with memorization of output contact pad posit

1990-11-21

1991-10-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

365104, 365185, 36518902, 36523003, 36523006, 365231, 371 103, G11C 700

Patent

active

050580680

ABSTRACT:
The disclosure concerns integrated memories and their redundancy circuits. The described redundancy concerns the memories organized in k groups of p columns (for example k=8 and p=64) to give words of k bits, when one column address out of p is chosen. The addresses of defective columns are memorized. In certain cases, the pad position (p0, p1, p2, p3) corresponding precisely to the defective column is also memorized. It is proposed to reduce the space occupied by the pad position determining logic circuits for which a redundancy has to be activated. This reduction is obtained by organizing a matrix EPROM to contain, for each defective column address, a memorized corresponding pad position. If there are N possibilities of repairs and r possible pad positions, the memory includes N lines and r columns. This is more than necessary, but that makes it possible to gain more space in avoiding the use of bulky logic decoders.

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K. E. Grosspietsch, "Schemes of Dynamic Redundancy for Fault Tolerance in Random Access Memories", IEEE Transactions on Reliability, No. 3, Aug. 1988, pp. 331-339.

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