Redundancy circuit of semiconductor memory device

Details Redundancy circuit of semiconductor memory device Redundancy circuit of semiconductor memory device

2001-12-18

2003-10-28

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S236000, C365S189050

Reexamination Certificate

active

06639854

ABSTRACT:

RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 2001-29101 filed on May 25, 2001, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit capable of detecting deterioration by interference of normal memory cell and redundancy memory cell while reducing detection time.
2. Description of the Related Art
FIG. 1
shows a conventional semiconductor memory device having a redundancy circuit with 64M bit capacitance. Referring to
FIG. 1
, the conventional semiconductor memory device having the redundancy circuit comprises: a memory cell array unit
50
of 64M bit for storing a plurality of data; a redundancy memory cell array unit
52
of 1K for recovering defective cells of the memory cell array unit
50
; and a sense amplification and I/O (input/output) control unit(s)
54
for sensing and amplifying read data received from the memory cell array unit
50
or from the redundancy memory cell array unit
52
and then outputting the amplified data to an I/O line or for sensing and amplifying write data received through the I/O line and then outputting the amplified data to the memory cell array unit
50
or to the redundancy memory cell array unit
52
.
The conventional semiconductor memory device further comprises: an address buffer unit
10
for receiving address signals A
0
~A
12
from an external source; a row address counter unit
12
for generating row address counter signals AR<
0
:
12
>; a row address buffer unit
14
for receiving the address signals A<
0
:
12
> from the address buffer unit
10
and the row address counter signals AR<
0
:
12
> from the row address counter unit
12
and generating row address data signals BXB<
0
:
12
>; a row predecoder unit
16
for receiving the row address data signals BXB<
0
:
12
> from the row address buffer unit
14
and generating decoded signals; and a row decoder unit
18
for decoding signals received from the row predecoder unit
16
and generating signals WL<
0
:
8191
> to select word lines of the memory cell array unit
50
.
The conventional semiconductor memory device further comprises: a command buffer unit
26
for receiving command signals i.e., row address strobe bar signal RASB, column address strobe bar signal CASB, write enable bar signal WEB, output enable bar signal OEB from external source(s); a command control unit
28
for receiving signals from the command buffer unit
26
; and a test mode control unit
30
for receiving signals from the command control unit
28
and the address signals A<
0
:
12
> from the address buffer unit
10
and generating test mode signals TRATX, TRATY to detect deterioration in word lines and bit lines of the redundancy memory cell array unit
52
.
The conventional semiconductor memory device further comprises: a row redundancy predecoder unit
20
for receiving row address data signals BXB<
0
:
2
> from the address buffer unit
14
and the test mode signals TRATX from the test mode control unit
30
and generating decoded signals TREB<
0
:
7
>; a row redundancy fuse unit
22
for generating signals REB<
0
:
7
> by programming row redundancy data; and a row redundancy enable signal generating unit
24
for receiving the decoded signals TREB<
0
:
7
> from the row redundancy predecoder unit
20
and the signals REB<
0
:
7
> from the row redundancy fuse unit
22
and generating signals RWL<
0
:
7
> to select word lines of the redundancy memory cell array unit
52
.
The conventional semiconductor memory device further comprises: a column address buffer unit
32
for receiving address signals A<
0
:
8
> from the address buffer unit
10
and generating column address data signals BYB<
0
:
8
>; a column predecoder unit
34
for receiving column address data signals BYB<
0
:
7
> from the column address buffer unit
32
and generating decoded signals; and a column decoder unit
36
for receiving the decoded signals from the column predecoder unit
34
, generating signals YS<
0
:
255
> to select bit lines of the memory cell array unit
50
and outputting the signals YS<
0
:
255
> to the sense amplification and I/O control unit
54
.
The conventional semiconductor memory device still further comprises: a column redundancy predecoder unit
38
for receiving a column address data signal BYB<
0
> from the column address buffer unit
32
and the test mode signals TRATY from the test mode control unit
30
and generating decoded signals TYREB<
0
:
1
>; a column redundancy fuse unit
40
for generating signals YREB<
0
:
1
> by programming column redundancy data; and a column redundancy enable generating unit
42
for receiving the decoded signals TYREB<
0
:
1
> from the column redundancy predecoder unit
38
and the signals YREB<
0
:
1
> from the column redundancy fuse unit
40
, generating signals RYS<
0
:
1
> to select bit lines of the redundancy memory cell array unit
52
, and outputting the signals RYS<
0
:
1
> to the sense amplification and I/O control unit
54
.
FIG. 2
is a circuit diagram of a part of the conventional row address buffer unit
14
for receiving the highest row address A<
12
> in FIG.
1
. As shown in
FIG. 2
, the row address buffer unit
14
comprises: an inverter
141
for receiving signals BP
4
K outputted from a command decoder (not shown) in a refresh operation; an inverter
142
for inverting signals received from the inverter
141
; an NMOS transistor Ni for discharging electric potential of a node Nd
1
that receives the highest row address signal AK<
12
> from the address buffer unit
10
according to the signals received from the inverter
142
to the ground voltage Vss; a PMOS transistor P
1
for transmitting a source voltage Vcc to a node Nd
2
when the signal of the node Nd
1
is at a low level; a PMOS transistor P
2
connected to the PMOS transistor P
1
in a row for applying the source voltage Vcc to its gate; NMOS transistors N
2
, N
3
connected between the node Nd
2
and the ground voltage Vss and their operation being controlled by signals of the source voltage Vcc and the node Nd
1
; an inverter
143
for inverting control signals XLAT; a clock inverter
144
for receiving signals of the node Nd
2
according to the control signals XLAT being active at a high level in all operations except for refresh and outputting the inverted signals to a node Nd
3
; an inverter
145
for receiving signals of the node Nd
3
and outputting the inverted signals to a node Nd
4
; an inverter
146
for receiving signals of the node Nd
4
and outputting the inverted signals to the node Nd
3
; a clock inverter
148
for outputting the highest row address signal AR<
12
> received from the row address counter unit
12
to the node Nd
3
according to control signal RLAT being active at a high level in a refresh operation; PMOS transistors P
3
, P
4
connected between the source voltage Vcc and a node Nd
5
in series and their operation being controlled by the ground voltage Vss and the node Nd
4
; an NMOS transistor N
4
connected between the node Nd
5
and a node Nd
6
and its operation being controlled by signals of the node Nd
4
; an inverter
149
for receiving signals BP
4
K outputted from a command decoder (not shown) in a refresh operation and outputting the inverted signals; an inverter
150
for inverting and outputting signals received from the inverter
149
; a NOR gate
151
for receiving signals received from the inverter
150
and the ground voltage Vss and outputting signals according to its NOR logic operation; a PMOS transistor P
5
connected between the source voltage Vcc and the node Nd
5
and for applying output signals of the NOR gate
151
to the gate; NMOS transistors N
5
, N
6
connected between the node Nd
5
and the ground voltage Vss in series and their oper

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