Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2009-12-31
2011-11-15
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S120000, C365S230010, C365S191000, C365S225700, C365S189070
Reexamination Certificate
active
08059477
ABSTRACT:
A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address.
REFERENCES:
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patent: 6950351 (2005-09-01), Lim
patent: 6977851 (2005-12-01), Noguchi
patent: 7397715 (2008-07-01), Lim et al.
patent: 2006/0092725 (2006-05-01), Min et al.
patent: 08-077790 (1996-03-01), None
patent: 10-0630527 (2006-09-01), None
patent: 1020070069367 (2007-07-01), None
Hynix / Semiconductor Inc.
Le Thong Q
William Park & Associates Ltd.
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