Redundancy circuit for semiconductor memory device

Details Redundancy circuit for semiconductor memory device Redundancy circuit for semiconductor memory device

1996-12-24

1998-06-16

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

365194, 3652257, G11C 500

Patent

active

057681970

ABSTRACT:
A redundancy circuit for a semiconductor memory device, comprising a first precharge transistor for transferring a precharge voltage to a first node in response to a first precharge signal, a second precharge transistor for transferring the precharge voltage transferred by the first precharge transistor to the first node in response to a second precharge signal, a first inverter for inverting a signal at the first node, an output terminal for transferring an output signal from the first inverter externally, a first NMOS transistor for transferring a supply voltage to the first node in response to a signal at the output terminal, a second inverter for inverting the second precharge signal, a second NMOS transistor for transferring a ground voltage to a second node in response to an output signal from the second inverter, a third NMOS transistor for transferring the ground voltage to the second node in response to the signal at the output terminal, a plurality of fourth NMOS transistors connected in parallel between the first and second nodes, for transferring a signal at the second node to the first node in response to an input address, and a plurality of fuses connected respectively between the first node and the fourth NMOS transistors, for programming a failed address.

REFERENCES:
patent: 4829480 (1989-05-01), Seo
patent: 4885721 (1989-12-01), Katanosaka
patent: 5461587 (1995-10-01), Oh
patent: 5469388 (1995-11-01), Park
patent: 5499214 (1996-03-01), Mori et al.
patent: 5574689 (1996-11-01), Morgan

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