Redundancy circuit for memory array and method for disabling...

Details Redundancy circuit for memory array and method for disabling... Redundancy circuit for memory array and method for disabling...

2005-08-09

2005-08-09

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070

Reexamination Certificate

active

06928009

ABSTRACT:
A redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

REFERENCES:
patent: 5930183 (1999-07-01), Kojima et al.
patent: 6078534 (2000-06-01), Pfefferl et al.
patent: 6272057 (2001-08-01), Koshikawa
patent: 6522595 (2003-02-01), Carson et al.
patent: 6694448 (2004-02-01), Callahan

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