Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-07-23
1996-04-02
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Bad bit
36518907, 371 103, G11C 2900
Patent
active
055047122
ABSTRACT:
Memories in integrated circuit form can have several amplifiers per data contact. To increase the possibilities of redundancy with a given number of redundancy columns without, causing too much space near the memory zone to be occupied by complicated multiplexers, the address AP used to select a single amplifier for each contact is used also to select one group of memories among several groups (as many groups as there are amplifiers per contact) in a defective address storage register. Only the defective addresses of this group are applied to a comparator used to detect whether a defective column address is received by the memory. A correlation is thus set up between the place where the defective column is located and the place where the redundancy column, which will be used to replace it, is located. This correlation results from the simultaneous selection by AP of a group of amplifiers and of a group of defective column addresses connected to these amplifiers.
REFERENCES:
patent: 4601019 (1986-07-01), Shah et al.
patent: 5107464 (1992-04-01), Sahara et al.
patent: 5140597 (1992-08-01), Araki
Nishimura et al, "A Redundancy Test-Time Reduction Technique in 1-Mbit DRAM with a Multibit Test Mode", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 43-49, IEEE, New York, USA.
Formby Betty
Groover Robert
SGS-Thompson Microelectronics S.A.
Yoo Do Hyun
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