Redundancy circuit for high speed EPROM and flash memory devices

Details Redundancy circuit for high speed EPROM and flash memory devices Redundancy circuit for high speed EPROM and flash memory devices

1990-10-24

1993-04-06

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 1140

Patent

active

052009220

ABSTRACT:
A redundancy control circuit enables the redundancy of a row or a column in a memory array such that no degradation in access time occurs. The redundancy circuit is further configured such that negligible power is consumed by the circuit during both a standby mode and a redundancy enable mode.

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