Redundancy circuit for a semiconductor memory device

Details Redundancy circuit for a semiconductor memory device Redundancy circuit for a semiconductor memory device

1984-11-08

1987-03-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 1140

Patent

active

046480757

ABSTRACT:
A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4393474 (1983-07-01), McElroy
patent: 4459685 (1984-07-01), Sud et al.
Y. H. Chan et al, "Array Word Redundancy Scheme", IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, pp. 989-992.
S. Konishi et al., "A 64 Kb CMOS RAM", ISSCC82, Feb. 12, 1982.
Japanese Patent Disclosure (KOKAI) No. 53-10228, Jan. 30, 1978.
Japanese Patent Disclosure (KOKAI) No. 53-41946, Apr. 15, 1978.

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