Redundancy circuit device

Details Redundancy circuit device Redundancy circuit device

1995-01-26

1996-07-23

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700

Patent

active

055396984

ABSTRACT:
The redundancy circuit device includes a main word line 1 for selecting a first memory area and a subsidiary word line 2, and a spare subsidiary word line 4 for selecting a second memory area (in which spare memory cells are arranged). In case a defective memory cell exists in the first memory cell area, the address is programmed by a redundancy program circuit 14 of a redundancy circuit 41 (provided for each section) of a section decoder 42. Further, when a row partial signal outputted from a row partial decoder 13 hits a defective memory cell, the spare subsidiary word line 4 is selected through the redundancy program circuit 14 to select the spare memory cell, without selecting the subsidiary word line 2. In a memory device of double word line system, a defective memory cell can be replaced with a spare memory cell in unit of each of a plurality of the subsidiary word lines connected to the main word line, thus improving the redundancy efficiency and thereby increasing the production yield of the memory chip.

REFERENCES:
patent: 5373471 (1994-12-01), Saeki

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