Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-12-30
2001-01-16
Nelms, David (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S145000, C365S189020
Reexamination Certificate
active
06175528
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a redundancy circuit for a semiconductor memory device.
DESCRIPTION OF THE PRIOR ART
As a high integration proceeds in a semiconductor memory device, lots of semiconductor memory cells are integrated in a chip. Even if one of memory cells is defected, the semiconductor memory chip is determined as a degraded semiconductor and cannot be used commercially. Thus, as an integration degree becomes higher, there becomes higher the probability that the memory chip is to be determined as a defected one, in fact it becomes almost impossible to manufacture the semiconductor memory chip with the economical efficiency. In order to solve these problems, employing a redundancy circuit is popular for this technique field.
The redundancy circuit consists of redundancy memory cells and redundancy address programming circuits. The redundancy memory cells and the redundancy address programming circuits are constituted at the semiconductor manufacturing process. The redundancy address programming circuit is programmed so that a redundancy memory cell would replace a memory cell, which is determined as a defected one at the test step. The above-mentioned programming operation is called as a “repair”, generally, this operation is processed by selectively cutting fuses contained in the redundancy address programming circuits by using a laser beam.
When a redundancy word line is to be used in order to access a plurality of the redundancy memory cells, a redundancy address programming circuit per each redundancy word line can be used, and a redundancy address bit programming circuit corresponding to an used address bit number can be contained in each redundancy address programming circuit.
FIG. 1
is a conventional redundancy address bit programming circuit, which utilizes a fuse.
Referring to
FIG. 1
, the redundancy address bit programming circuit depicted in
FIG. 1
is a circuit generally constituted one by one in response to each address bit. Therewith, the input signals are designated by POWER-UP, a corresponding address bit signal A, and a its reversed address bit signal /A, while the output is represented by a character of Q. The redundancy address bit programming circuit contains transmission gates T
2
and T
4
, an inverter INV
2
, a fuse F
2
, and NMOS transistors N
2
and N
4
.
In
FIG. 1
, a fuse F
2
may be programmed—selectively cut—in accordance with the bit corresponding to an address of a defected cell. As can be seen in
FIG. 2
, the input signal POWER-UP increase when a power is supplied, then the input signal POWER-UP drops suddenly and keeps in “low’ level. Referring to the case that the fuse is cut, an NMOS transistor N
4
becomes turn-on by the high level of the input signal POWER-UP inscribed to the NMOS transistor N
4
's gate. Accordingly, a node NA becomes low level, the transmission gate T
2
becomes turn-on, and the transmission gate T
4
becomes turn-off, then the address bit signal A is outputted to Q. On the other hand, the “low” level of the node NA becomes reversed, i.e., as “high” level, thereafter the reversed “high” level signal is inscribed to NMOS transistor N
2
's gate. So, the NMOS transistor N
2
becomes turn on, then the node NA keeps stable as “low” level. That is, even though the power-up becomes again “low” level after a certain time, the node NA level keeps stable by a latch that consists of the inverter INV
2
and the NMOS transistor N
2
.
On the contrary, referring to the case that a fuse F
2
is not cut, the node NA may have the distributed voltage level in accordance with each resistance value of the fuse F
2
and the NMOS transistor N
4
. Generally, since the fuse F
2
is constituted from the conductive poly-sillicon, the level of the node NA has the level of the voltage signal VDD. Since the level of the node NA is latched by the inverter INV
2
and the NMOS transistor N
2
, the transmission gate T
2
becomes turn-off and the transmission gate T
4
becomes turn-on by the “high’ level of the node NA, then the reversed address bit signal /A is outputted.
FIG. 3
shows the redundancy address programming circuits containing the address bit programming circuits, such as those of
FIG. 1
, which is a circuit for programming the memory cells coupled in a line of the redundancy word for the address of the defected memory cells. Herein, for the sake of convenience, the address of only 4 bits would be explained.
Referring to
FIG. 3
, the redundancy address programming circuit is provided with four redundancy address bit programming circuits
102
,
104
,
106
and
108
, a redundancy master programming circuit
100
, NAND gates ND
2
, and ND
4
, and a NOR gate NR. Four fuses of the redundancy address bit programming circuits
102
,
104
,
106
and
108
are programmed in accordance with an address bit corresponding to each defected memory cell. For example, if an address of a defected memory cell is “1001”, the fuses in redundancy address bit programming circuit
104
and
106
remains not cut, the fuses in the redundancy address bit programming circuit
102
and
108
are cut. The redundancy master programming circuit
100
includes a master fuse FM, NMOS transistors N
6
and N
8
, and an inverter INV
4
. If the master fuse FM is cut, the output M becomes a “high” level, if not, the output M becomes a “low” level. As a result, the maser fuse FM in the redundancy master programming circuit
100
can be programmed, according as whether a redundancy memory cell would be used or not.
In
FIG.3
, a redundancy word line selection signal RWL can be outputted by executing the logic multiplication process from the NAND gates ND
2
and ND
4
and the NOR gate NR
2
. Accordingly, if signals Q
0
, Q
1
, Q
2
, Q
3
, and M are all “high” level, the redundancy word line selection signal RWL becomes a “high” level, if not, the RWL becomes “low”level. As a result, if the address of the defected memory cell is inputted, i.e., A
0
, A
1
, A
2
, A
3
are 1, 0, 0, 1 in sequence, the RWL becomes a “high” level.
However, there is a problem that the conventional redundancy programming circuit is to need high-priced laser equipments for the above fuse programming, so there exists a demerit that the manufacturing cost becomes higher.
SUMMARY OF INVENTION
It is, therefore, an object of the present invention to provide a redundancy address bit programming circuit of a semiconductor memory device for rapidly and easily repairing a defected cell without the help of high-priced laser equipment.
It is another object of the present invention to provide a redundancy address programming circuit of the semiconductor memory including the redundancy address bit programming circuits.
In accordance with an embodiment of the present invention, there is provided a redundancy address bit programming circuit including a redundancy memory cell, comprising: program pads for providing signals to first and second program nodes; a ferroelectric capacitor programmed according to a bit value corresponding to a defected address, coupled between the first and second nodes; a load capacitor coupled between the second program node and a ground; a power-up signal generator means for generating a power-up signal to be coupled to the first program node, wherein the power-up signal follows a level of a power signal at a beginning of a power signal supply, and is maintained as a ground level during a stable level state of the power signal supply; a latch means for latching the second program node signal at the beginning of the power signal supply and outputting a latched signal during the stable level state of the power signal supply; and a multiplexer for selectively outputting one of an address bit signal and a reversed address bit signal in response to the latched signal.
In accordance with another embodiment of the present invention, there is provided a redundancy address programming circuit for use in a semiconductor memory device, comprising: a) a power-up generator means for generating a power
Ho Hoai V.
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Nelms David
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