Redundancy circuit and method of ferroelectric memory device

Details Redundancy circuit and method of ferroelectric memory device Redundancy circuit and method of ferroelectric memory device

1999-06-30

2000-12-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365145, 36523006, G11C 700

Patent

active

061575852

ABSTRACT:
There is provided a redundancy circuit of a ferroelectric memory device capable of performing a repair software-wise, the redundancy circuit of a ferroelectric semiconductor device having an address buffer, a normal decoder, a normal memory cell array and a redundancy circuit, said redundancy circuit comprises: a redundancy memory cell array; a first programming unit for storing a fail address signal; a second programming unit for storing a fail number signal; a controller for generating control signals which control the first programming unit and the second programming unit; an address comparator for comparing the fail address stored in the first programming unit with the address of the address buffer; and a redundancy decoder for activating the normal memory cell array or the redundancy memory cell array, according to the address of the address buffer, the output signal of the address comparator and the output signal of the second programming unit. Also, a redundancy method is disclosed.

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patent: 5812466 (1998-09-01), Lee et al.
patent: 5828599 (1998-10-01), Herdt
patent: 5862086 (1999-01-01), Makimura et al.

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