Redundancy circuit and method for semiconductor memory devices

Details Redundancy circuit and method for semiconductor memory devices Redundancy circuit and method for semiconductor memory devices

2002-05-31

2004-05-04

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185090, C365S230060

Reexamination Certificate

active

06731550

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to redundant circuitry for memory devices, and particularly to a redundancy scheme in which defective memory cells are individually replaced.
2. Description of the Related Art
Processing defects in memory devices, such as static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices, can significantly reduce the processing yield in large scale memory arrays. In order to improve the processing yield of memory chips, various methods of error correction have been created. These include ‘soft’ error correcting whereby software corrects for physical defects, and ‘hard’ error correcting whereby defective circuit elements are replaced with redundant elements included on the chip. The use of soft or hard error correcting can result in lower chip manufacturing costs and earlier introduction of new products on existing wafer fabrication lines or in new process technologies.
Yield enhancement by ‘hard’ error correcting on a memory chip is typically produced by including redundant rows and/or columns within the memory array. A few redundant rows or columns can significantly enhance yield of a memory circuit since many devices are rejected for single bit failure or failures in a single row or column. These redundant rows or columns can be added to the memory design to replace defective rows or columns which are identified at electrical test after wafer processing.
To replace a defective memory row or column, the defective row or column is first disconnected from the array. This is accomplished by one of three methods: current blown fuses, laser blown fuses, and laser annealed resistor connections. Then a redundant row or column is enabled and programmed with the defective row or column address.
Although this use of redundant rows and columns of memory cells increases product yield, many times the dominant failures in a memory device are isolated in nature and primarily cause individual memory cells to fail. Without entire rows or columns of memory cells failing, most of the redundant memory cells appearing in existing memory devices are unused, resulting in wasted silicon space in the memory device.
Based upon the foregoing, there is a need for a redundancy technique for memory device that more efficiently remedies a majority of failing memory devices.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome shortcomings associated with existing redundancy techniques and satisfy a significant need for a more efficient way to replace defective memory cells in a semiconductor memory device. Defective memory cells are individually replaced. Instead of providing entire rows and/or columns of redundant memory cells, only a limited number of redundant storage elements are needed in the memory device in order to suitably replace isolated memory cells that are defective.
According to an exemplary embodiment of the present invention, a memory device includes at least one redundant storage circuit capable of storing a data value, and redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device and generating an output signal having a value indicative of an input address corresponding to the address of the defective memory cell. The memory device further includes circuitry for individually replacing the defective memory cell with the redundant storage circuit during a memory access operation based upon the value of the output signal of the redundant decode circuitry. By individually replacing the defective memory cell with a single redundant storage circuit, the memory device is capable of efficiently handling isolated defects occurring within the array of memory cells in the memory device.
An operation of the memory device includes receiving an address input during a memory access operation, determining whether the address input corresponds to a defective memory cell, identifying the individual external data signal to connect to the redundant storage circuit, and individually connecting the identified external data signal to the redundant storage circuit.


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patent: 6542420 (2003-04-01), Takase
patent: 6563759 (2003-05-01), Yahata et al.

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